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How to increase the memory capacity of the IP core fifo_generator in Vivado 2018.3?

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Cesar0182

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Greetings ... tell them that I am new using the IP cores in Vivado, and I would like to know if it is possible to increase the memory capacity of the fifo_generator IP core v13.2? And how is the correct way to do it ?.
 

the ram size settings are set in the GUI when you generate the FIFO.
 

I commented that the way I'm checking is through the simulation, where you are using 26 fifos with a 52-bit write and read bus, as far as I understand the fifos (fifo_generator v13.2) of my system supports a limited amount of data packets, as the number of packages increases, the data begins to be overwritten. To monitor, there is a record that indicates the available space in the fifo, in addition to the data flow of the system's output. Initially I increased the value of Write Depth from 512 to 1024 (the truth is not sure if it is the correct parameter) and only send 4 packages (the minimum), but at the exit of the fifos the last data packet is lost as It is shown in the attached image.

write_depth_1024_4packets.PNG


I leave attached the IP that I am using and the vhdl code where I use the fifos.
 

Attachments

  • g1_wbus_client_fifos_vhdl.zip
    2.5 KB · Views: 66
  • g1_ipcat_wbus_client_fifo.zip
    14.3 MB · Views: 84

You change the depth & width parameters to get the FIFO size of your choice in Vivado. These options are typically in the 2nd tab, under 'Data Port Parameters' field.

Untitled.png
 

I already commented that I made the change only of Write Depth from a value of 512 to 1024 (as shown in the attached image), but this has not worked for me, I'm still trying to see the problem in the waveforms I get in the simulation.

customize_ip.PNG
 

Make sure the core is regenerated and the new one is used in your project.
From the IP Sources tab, for the FIFO IP, also verify under Instiantiation Template, that in the generated *.vho file, the changes for the FIFO are reflected.
 

That's odd, I posted yesterday about what the issue was but there isn't a post, must have forgot to click the post button.

Anyway the problem is in your constant for Almost_Full_Depth:
Code:
CONSTANT Almost_Full_Depth : std_logic_vector(9 downto 0) := "0111110100";
which translates to 500, which means your code is still treating the FIFO as being 512 deep.

FYI, for the previous posters the FIFO was reconfigured to be 1024 just open the zip file of the FIFO IP directory and look at the xci file.
 

That's odd, I posted yesterday about what the issue was but there isn't a post, must have forgot to click the post button.

Anyway the problem is in your constant for Almost_Full_Depth:
Code:
CONSTANT Almost_Full_Depth : std_logic_vector(9 downto 0) := "0111110100";
which translates to 500, which means your code is still treating the FIFO as being 512 deep.

FYI, for the previous posters the FIFO was reconfigured to be 1024 just open the zip file of the FIFO IP directory and look at the xci file.

thanks for the help Ads-ee ... you suggest that you increase the value of Almost_Full_Depth ?. As for the .xci file, do I need to modify some value?
 

I told you that I made the change of the variable Almost_Full_Depth = 1000, but I still do not have any change .... reviewing the waveforms of a particular fifo (u_client (0)), where apparently is the only one used and in this I have observed certain differences between a correct simulation and the one that is failing, although I am not using the same simulator can give an idea of ​​the failure, where the empty and valid signals of the failed simulation do not return to 1 and 0 respectively as observed in the correct simulation.

Passed Simulation

passed_sim_512.PNG

Failed Simulation

failed_sim_1024.PNG
 

thanks for the help Ads-ee ... you suggest that you increase the value of Almost_Full_Depth ?. As for the .xci file, do I need to modify some value?

No I was just commenting on the fact that the core generated as a 1024 deep FIFO, which can be seen by looking at the .xci file contents.
Code:
        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">1024</spirit:configurableElementValue>
        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:configurableElementValue>

- - - Updated - - -

I think there may be something very wrong with how you are testing this. What kind of testbench are you using? Are you using fixed delays with wait for ## ns statements? (I recall you were using VHDL)

FYI, I'm asking this because I know for certain Vivado's simulator does scheduling different than Modelsim when there is a mix of using wait for delays in a testbench where the testbench signals change on the clock edge. If a testbench is properly written both simulators will give identical results. I've seen this happen when trying to run other engineer's testbenches in Vivado's simulator where signals are manually toggled in the testbench using wait delays between assignments.
 

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