Follow along with the video below to see how to install our site as a web app on your home screen.
Note: This feature may not be available in some browsers.
Code VHDL - [expand] 1 2 3 my_loop: for i in 0 to 7 generate my_assignment(3*i) <= my_signal(3*i); end generate;
How can I use statement " For - Generate" in VHDL with step other than one ?
How can I use statement " For - Generate" in VHDL with step other than one ?
...
architecture generations of your_entity is
-- make component declaration(s) for structural here
-- make signal declaration(s) here
-- make other declaration(s) here
begin
outer(row)_generate_label : for row_index in row_width_start to row_width_stop generate
begin
inner(column)_generate_label : for column_index in column_width_start to column_width_stop generate
-- make possible declarations here
begin
-- code for unit here (behavioural or structural)
end generate inner(column)_generate_label;
end generate outer(row)_generate_label;
end architecture generations;