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[SOLVED] for generate with step other than one

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Mai89

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How can I use statement " For - Generate" in VHDL with step other than one ?
 

Just multiply the index, e.g. step size of 3 instead of 1
Code VHDL - [expand]
1
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my_loop: for i in 0 to 7 generate
    my_assignment(3*i) <= my_signal(3*i);
end generate;
 
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The nested for-generate statement

Mai89 said:
How can I use statement " For - Generate" in VHDL with step other than one ?
Click to expand...

The outer generate statement generates the rows. The inner generate statement generates the units in each of the rows as columns.

Code: 
...
architecture generations of your_entity is
-- make component declaration(s) for structural here
-- make signal declaration(s) here
-- make other declaration(s) here

begin

    outer(row)_generate_label : for row_index in row_width_start to row_width_stop generate
    begin

         inner(column)_generate_label : for column_index in column_width_start to column_width_stop generate
               -- make possible declarations here
         begin

               -- code for unit here (behavioural or structural)

         end generate inner(column)_generate_label;

    end generate outer(row)_generate_label;

end architecture generations;
 
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