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Post-layout Simulation Errors in Virtuoso with av_extracted view

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minmin_J

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Hi,

Recently I am doing the post_layout simulation. The av_extracted file generated by AssuraQRC is attached to the pre_layout schematic.

However, the simulation reported the following error (virtuoso ADE explorer):
Errors were discovered by the ghost during the flattening of the hierarchy.
Error (SFE-46): "input.scs" 3745324: The instance of `I4': `xxx' can have up to 6 terminals (but there are 78).

The content of the corresponding line of the post_layout simulation netlist input.scs is:
I4 (vdd!0 address\<7\>address\<6\>address\<5\>address\<4\> \
Address \ <3 \>Address\ <2 \>Address\ <1 \>Address\ <0 \> clk cs \
Read_data \ <31 \> read_data \ <30 \> read_data \ <29 \> read_data \ <28 \> \
Read_data \ <27 \> read_data \ <26 \> read_data \ <25 \> read_data \ <24 \> \
Read_data \ <23 \> read_data \ <22 \> read_data \ <21 \> read_data \ <20 \> \
Read_data \ <19 \> read_data \ <18 \> read_data \ <17 \> read_data \ <16 \> \
.....
Click to expand...
According to the error, it seems that only the single-bit port is recognized but not the bus ports. The following is the pre-layout netlist:

Code: 
Module aes (clk, reset_n, cs, we, address, write_data, read_data, VDD, VSS);
Enter the [7:0] address;
Input [31:0] write_data;
Output [31:0] read_data;
Enter clk, reset_n, cs, we;
Input VDD, VSS;
...
I don't know how to fix this problem. Does anybody know about this situation? Thanks in advance.
 

You have 78 terminals but only 6 defined in the subcircuit. I don't have enough knowledge about verilog/vhdl, however define buses width explicite in the module definition.
 

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