garvind25
Full Member level 3
Hi,
I was making a project where I needed to drive an I/O pin of a CPLD as input for logic 0 or logic 1 as required through a SPDT switch. I am planning to make the connection as in the figure.
I am in dilemma as to how to select the value of resistor R? For an I/O pin, what will be the current that will be pushed to GND or pulled from VCC_3.3v? The CPLD datasheet can be found here. I will be operating the CPLD in LVCMOS 3.3v standard at 25 or 50 MHz (frequency not finalised yet).
I am asking this question as if I select it to a low value (like 100-500 ohms) , the I/O pin can source or sink a large current, wasting board power supply. Also, if I select it to a large value (like 10k-1M ohms), when the switch connects the I/O pin to logic high (3.3v) or logic low (0v), there can be a big voltage drop at the resistor leaving a smaller voltage for the I/O pin (which may not be correctly interpreted as logic 1 or logic 0).
Awaiting your comments.
Thanks and regards,
Arvind Gupta
I was making a project where I needed to drive an I/O pin of a CPLD as input for logic 0 or logic 1 as required through a SPDT switch. I am planning to make the connection as in the figure.
I am in dilemma as to how to select the value of resistor R? For an I/O pin, what will be the current that will be pushed to GND or pulled from VCC_3.3v? The CPLD datasheet can be found here. I will be operating the CPLD in LVCMOS 3.3v standard at 25 or 50 MHz (frequency not finalised yet).
I am asking this question as if I select it to a low value (like 100-500 ohms) , the I/O pin can source or sink a large current, wasting board power supply. Also, if I select it to a large value (like 10k-1M ohms), when the switch connects the I/O pin to logic high (3.3v) or logic low (0v), there can be a big voltage drop at the resistor leaving a smaller voltage for the I/O pin (which may not be correctly interpreted as logic 1 or logic 0).
Awaiting your comments.
Thanks and regards,
Arvind Gupta