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    Connecting a SPDT switch to I/O pin of a CPLD

    Hi,

    I was making a project where I needed to drive an I/O pin of a CPLD as input for logic 0 or logic 1 as required through a SPDT switch. I am planning to make the connection as in the figure.

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    I am in dilemma as to how to select the value of resistor R? For an I/O pin, what will be the current that will be pushed to GND or pulled from VCC_3.3v? The CPLD datasheet can be found here. I will be operating the CPLD in LVCMOS 3.3v standard at 25 or 50 MHz (frequency not finalised yet).

    I am asking this question as if I select it to a low value (like 100-500 ohms) , the I/O pin can source or sink a large current, wasting board power supply. Also, if I select it to a large value (like 10k-1M ohms), when the switch connects the I/O pin to logic high (3.3v) or logic low (0v), there can be a big voltage drop at the resistor leaving a smaller voltage for the I/O pin (which may not be correctly interpreted as logic 1 or logic 0).

    Awaiting your comments.

    Thanks and regards,
    Arvind Gupta

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    Re: Connecting a SPDT switch to I/O pin of a CPLD

    Wow.

    How much current do you think the input draws?

    Have you actually looked at the data sheet?

    You could actually do this with a SPST switch, you know.

    You don't need that resistor.



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    Re: Connecting a SPDT switch to I/O pin of a CPLD

    I presume, the switch control input has high impedance and no static current is expected to flow. You'll usually place no series resistor, or if driving a high frequent switching signal, a trace impedance matching resistor.


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    Re: Connecting a SPDT switch to I/O pin of a CPLD

    See this excerpt from the datasheet.

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    The input has a high impedance like you have been told. You do not need a current-limiting resistor for a pin used as an input.
    -------------
    --Akanimo.


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    Re: Connecting a SPDT switch to I/O pin of a CPLD

    Not the question you asked but you will need to take contact bounce into account when you try to detect the change.
    The 'classic' approach is to use a resistor from VCC to the switch with the other side of the switch to ground. You then look at the junction of the resistor and switch. (Of course you can swap the switch and resistor around - depends if you want a high or a low when the switch is open.) The size of the resistor depends on the leakage/drive current of the IO pin and how much current you can allow when the switch is closed but can often be around 10K.
    Susan


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    Re: Connecting a SPDT switch to I/O pin of a CPLD

    Normally for SPST switches, we use a current limiting resistor in the arm without the switch to prevent shorting the supply voltage to GND when the switch is CLOSED but we do not current-limit the arm that the switch is placed. This allows the resistor to pull the pin to either 0V or Vdd when the switch is OPEN depending on which arm the resistor is placed.
    -------------
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    Re: Connecting a SPDT switch to I/O pin of a CPLD

    Thanks for all the inputs. I did go through the datasheet. But the comments in the parameter section for IIL and IHL were confusing (especially for IIH: I/O High Z leakage. What does it mean). Anyways, as confirmed by many, the current pushed or pulled by the I/O pin when used as an input is very less and hence I need not put a current limiting resistor.

    Coming to switch denouncing, pls. suggest a simple debouncing technique for using with SPDT switch for providing logic 0 or 1 as input when required. I am using a 3 pin SPDT as I can directly connect the input pin to either 3.3v or 0v when ever required. Also using a SPDT avoids shorting the VCC to Gnd.

    Thanks again,
    Arvind Gupta



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    Re: Connecting a SPDT switch to I/O pin of a CPLD

    Hi,

    for IIH: I/O High Z leakage. What does it mean
    There is no need for a current. Thus ideally the current is zero. But any semiconductor and/or the isolation will "leak" a little current (especially at high temperature the silicone becomes conductive).

    Debouncing can be made with RC circuitry, even better if combined with a schmitt trigger,
    Or it can be made within the CPLD.
    Many solutions have been discussed here in the forum and even more in the internet. Just do a search.

    May I ask: Why SPDT? Why no SPST with pullup/pulldown?

    SPST, may be (while a SPST doesn´t)
    * "break befor make" --> this results in a small time of floating node.
    * "make before break" --> this results in short circuit of the power supply. You need to safely avoid this.

    Klaus
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    Re: Connecting a SPDT switch to I/O pin of a CPLD

    Quote Originally Posted by KlausST View Post
    Hi,

    May I ask: Why SPDT? Why no SPST with pullup/pulldown?

    SPST, may be (while a SPST doesn´t)
    * "break befor make" --> this results in a small time of floating node.
    * "make before break" --> this results in short circuit of the power supply. You need to safely avoid this.

    Klaus
    I will be using a 3 pin 2 position SPDT. So either the CPLD pin will connect to VCC or to GND. At no time the VCC will be shorted to GND (in SPST case, when the switch is connecting the pin to VCC, it will connect the VCC to the GND also. Even if a pull up resistor is available, there will be current flowing from supply to pull up / pull down resistor to GND. )

    Regarding the switch bouncing, due to break and make operations every time the logic voltage is changed, yes that will be there. To avoid it, I am looking for a suitable debouncing circuit.

    Thanks,
    Arvind Gupta.



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    Re: Connecting a SPDT switch to I/O pin of a CPLD

    Hi,

    Even if a pull up resistor is available, there will be current flowing from supply to pull up / pull down resistor to GND. )
    Yes, that´s the meaning of a pullup/pulldown resistor. Without current flow the resistor is useless. (Even if the current is just the leakage current of the I/O)

    Klaus
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