Frequency range selector

Hi ,
Can you explain how this circuit is working? This is a frequency range selector circuit which is being used in the DLL. Its output is 2 bit select signal which is used to select the operating range.
Td clock frequency = 0.5* reference clock.
thanks

I think you're not giving us all the information. Where is refclk used? What drives the latches?

It looks like when tdc goes high a bunch of logic "1"s propogate through the delay line so that at some point all the outputs are high. This circuit, as shown, doesn't make much sense to me.

barry said:

I think you're not giving us all the information. Where is refclk used? What drives the latches?

It looks like when tdc goes high a bunch of logic "1"s propogate through the delay line so that at some point all the outputs are high. This circuit, as shown, doesn't make much sense to me.

Click to expand...

Hi, you can refer to this paper.
https://ieeexplore.ieee.org/abstract/document/1657135

Without knowing the value of the delays in the delay line, there's no way of analyzing this. I have no idea how the authors made the leap to the statement: "when the reference clock is 100 MHz, the outputs of the encoder are bit streams of “1110” "

I believe it can work but as previously stated, much of the detail is missing.
The frequency selector seems to be a 'window' detector, able to tell which range the input frequency lies in. The wave propagating along the delay line will produce a cyclical pattern of bits which can be recognized by the encoder.

Brian.

Can you comment on how this encoder is working? I mean the pulse width from first to tenth of "and " gate will be decreasing. How is encoder sensing and how it is being able to give two stable outputs s1 and s0.

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barry said:

Without knowing the value of the delays in the delay line, there's no way of analyzing this. I have no idea how the authors made the leap to the statement: "when the reference clock is 100 MHz, the outputs of the encoder are bit streams of “1110” "

Click to expand...

And which type of encoding is done? As on 10 inputs are there and for 100MHz the encoder bit streams are 1110

I mean the pulse width from first to tenth of "and " gate will be decreasing

Click to expand...

I'm not sure it is.
The top section is a delay line (of unknown delay) and whatever signal goes in (tdc_clk) eventually comes out the same at the 'o10' output. The intermediate steps hold samples of the signal after the delay period of each tap in the delay chain. I think all the encoder is supposed to do is recognize the patterns of the bits leaving the delay taps and set the S0 and S1 bits accordingly.

There is nothing to suggest the input is a square wave and the delays could be short enough that even at tap 10 only one cycle of input would have propagated through. More information on the delay periods and input wave shape is needed to be sure my prognosis is correct.

Brian.

Akshaay said:

Can you comment on how this encoder is working? I mean the pulse width from first to tenth of "and " gate will be decreasing. How is encoder sensing and how it is being able to give two stable outputs s1 and s0.

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And which type of encoding is done? As on 10 inputs are there and for 100MHz the encoder bit streams are 1110

Click to expand...

Not exactly. The way this works is as follows: The clock input goes high. Sometime later (whatever that undefined delay is) the first AND output goes high (and stays high). After two delays, the second AND goes high, and so on. Presumably, when the clock goes low (this is missing from the crappy document), the 10 AND outputs are latched. Four of those outputs are applied to the decoder, which outputs a 2-bit code.

Just my guessing.
The clk pass through delay lines and sampled at the latch(i think it should be a flipflop instead of latch) of a refclk. With the refclk, we can get a code which representing how big is the delay of delay lines.
The control unit is hard-decoded into two bits, still representing delaylines to decide what frequency to operate.