Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Parasitic capacitor extraction: huge value

Status
Not open for further replies.

Anomis

Junior Member level 3
Joined
Mar 11, 2017
Messages
29
Helped
5
Reputation
10
Reaction score
4
Trophy points
3
Location
South Korea
Activity points
294
Hi everybody,
I am playing with 65nm samsung process and do explore some parasitics components in the straightforward testbench below:
But the extracted cgsl(overlap capacitance between gate and lightly-doped source region) seems to be highly huge here : 96pF, that shall short G and S @high frequency design ( the model employed in this process here i guess could be the BSIM4). It is so weird.
could anybody have expertise in this stuff? please help me
2019-05-30_17-55-58.jpg
thank you!!
 

This doesn't make sense. Your transistor is not big and still, I see besides pF values, also mF, if I read it correctly.
 

This doesn't make sense. Your transistor is not big and still, I see besides pF values, also mF, if I read it correctly.

Hi sutapanaki,
However, my question is : with such huge value, there could be a problem in RF design ?, it will short G n S together, for example, Zgs ~ 0 Ohm @2.4 GHz
Does it make sense? or i dont fully understand what inside this model.
here is my another capture to show that kind of big value.
para.jpg
Thanks,
 

Before thinking about problems in RF design with these transistors, I would worry about models, their possible incorrectnes and my lack of understanding what's going on inside.
 

You show schematic only, but talk about parasitic capacitance.
Is this schematic simulation problem, or post-layout?
 

You show schematic only, but talk about parasitic capacitance.
Is this schematic simulation problem, or post-layout?

Hi timof, this is about pre-layout simulation, even though my performance at 2.4 GHz looks good but the parasitics extracted by model here make me confused,
I don't know what the problem is, in my intuition, the parasitics at 65 nm should be around a few of hundred fF telling us a good truth for such dimension
 

Why don't you just simulate Cgs and Cgd and see for yourself what the value is.
 

Why don't you just simulate Cgs and Cgd and see for yourself what the value is.
Hi Sutapanaki, could you explain how do we simulate for Cgs and Cgd?

There is so much confusion around for me.
1. I can use tran simuation and find the time domain signal and verify the waveform. But this includes resistance also, so we cant directly get the Cgs and Cgd value.
2.we can use AC analysis by giving Vsin source with AC magnitude =1 and get the V/I. Again this includes resistance
3.I use mostly S parameter simulation to get the impedance and find the total capacitance from it. But this doesnt give Cgs and Cgd value individually.
4. I am not sure how to use DC simualaion for this purpose.
 

Hi everybody,
I am playing with 65nm samsung process and do explore some parasitics components in the straightforward testbench below:
But the extracted cgsl(overlap capacitance between gate and lightly-doped source region) seems to be highly huge here : 96pF, that shall short G and S @high frequency design ( the model employed in this process here i guess could be the BSIM4). It is so weird.
could anybody have expertise in this stuff? please help me
View attachment 153382
thank you!!

I don't think that value is unrealistic. For example, in PTM from ASU (http://ptm.asu.edu/modelcard/HP/22nm_HP.pm) I see similar values. But what you have printed is the model parameters (parameters that are put in the model files). Print the DC operating parameters and check the value you get there.
 

Hi Sutapanaki, could you explain how do we simulate for Cgs and Cgd?

There is so much confusion around for me.
1. I can use tran simuation and find the time domain signal and verify the waveform. But this includes resistance also, so we cant directly get the Cgs and Cgd value.
2.we can use AC analysis by giving Vsin source with AC magnitude =1 and get the V/I. Again this includes resistance
3.I use mostly S parameter simulation to get the impedance and find the total capacitance from it. But this doesnt give Cgs and Cgd value individually.
4. I am not sure how to use DC simualaion for this purpose.

Well, I think I found an answer for my question. https://www.edaboard.com/showthread...culate-input-capacitance-of-a-2-ports-network
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top