Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Post synthesis simulation shows setup and hold time violations while DC doesn't

Status
Not open for further replies.
D

dormant_bci

Newbie
Joined
Feb 4, 2018
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
47
Dear all

I've synthesized my design in DC and optimized for delay. According to the reports, there are no negative slack times, nor any time violations. But when I do the post-synthesis simulation in ModelSim, there are lots of setup and hold time violations.

My design has two clock domains but got separated using flip flops. In some flip-flops, I'm using the negative edge of the clock and in some others, I use the positive edge.

What causes this?
 

dormant_bci said:
My design has two clock domains but got separated using flip flops. In some flip-flops, I'm using the negative edge of the clock and in some others, I use the positive edge.

What causes this?
Click to expand...

The difference is between one output (Q) or the other (not Q). You can take the positive going edge or the negative going edge. (A counter goes down by taking Q from the flip-flops. It counts up by taking not-Q.)

I don't know if this is the cause of your error messages.
 

I have seen over and over folks failing to setup a gate level simulation that makes sense. Have you done this type of task before?
 

I had done it before for smaller designs. But my current design is a processor with lots of flip-flops, connections and state machines. The problem is that the synthesizer's report shows no time violation, but Modelsim does. The funny thing is that with much lower frequency the simulation is okay. But as I increase the frequency (in simulation), it gives setup and hold time violations.
 

dormant_bci said:
I had done it before for smaller designs. But my current design is a processor with lots of flip-flops, connections and state machines. The problem is that the synthesizer's report shows no time violation, but Modelsim does. The funny thing is that with much lower frequency the simulation is okay. But as I increase the frequency (in simulation), it gives setup and hold time violations.
Click to expand...

My first guess is that you are not using SDF files. The fact that increasing the frequency triggers hold violations is very suspicious.
My second issue is that you are using simulation to validate timing. That doesn't scale, we just can't afford to do chip-level netlist simulations anymore.
 

I do use the SDF file, or the post-synthesis simulation will have no sense.
Why do you say "That doesn't scale, we just can't afford to do chip-level netlist simulations anymore.That doesn't scale, we just can't afford to do chip-level netlist simulations anymore." ?
Why can't we afford to do that?
Post-synthesis simulation is used to validate the design for ASIC synthesis, isn't it?
 

dormant_bci said:
I do use the SDF file, or the post-synthesis simulation will have no sense.
Why do you say "That doesn't scale, we just can't afford to do chip-level netlist simulations anymore.That doesn't scale, we just can't afford to do chip-level netlist simulations anymore." ?
Why can't we afford to do that?
Post-synthesis simulation is used to validate the design for ASIC synthesis, isn't it?
Click to expand...

Nope. You trust your STA and your LVS. Avoid gate-level simulations at all costs.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top