Aspect ratio of the matched transistor array

Dear friends,

From the layout perspective, a better matching can be achieved when the array of the matched transistor is becoming square (aspect ratio) . my question is, so we look to the array aspect ratio including the wiring or that is only considered for the transistors

Thank you

Pelgrom’s law states that matching gets better with increasing gate area, so I wouldn’t necessarily say that a “square aspect ratio” has optimal matching. As an example, a set of devices sized to be 2um/2um will not match as well as a set of 10um/6um devices. And if you have to reduce gate area significantly to increase the number of fingers to achieve a square shape, matching will also suffer.

To answer your question, the impact of interconnect tends to be situational. Depending on your application, interconnect matching may also be a critical factor. It may not be so much of a consideration for a low current FET differential pair in a low frequency design. But if you have a high current npn differential pair, mismatches in the interconnect can result in mismatch/performance degradation due to the base currents. Source resistance mismatch in high current current mirrors will also translate to mismatch, so that’s another situation you might want to common centroid/match impedances of interconnect.

Even if you have a single transistor, with wide gate, it is recommended to fold its gate to form a multi-finger device, with aspect ratio around 1.

Interconnects matching is important not only from the viewpoint of resistance matching (or IR drop, or metal debiasing), but also from the viewpoint of capacitance matching, or delay matching - of course, that all depends on the requirements, on the circuit, and on the application, as ljp2706 correctly mentioed.

Dear friends,

Thank you for your contribution to my post

I would say that I usually try to have aspect ratio less than than 10 in my design. but yes you are right, sometimes it is becoming difficult to achieve it specially with big transistors.

Now I have a question related to that, if in the case of big transistors, is it better to increase the order of the matching array to reduce the unit cell off the transistor size. or it is better to increase the number of fingers and keeping the same order of the array

Example ;

Suppose two big transistors A and B.

what is better matching array

ABBA/BAAB with number of fingers = 4

or ABBAABBA/BAABBAAB with number of gates = 2

Note : both of the array are two dimensional array

Thank you very much

Just a comment, in the first example, A and B both have 4 gates. In the bottom, A and B both have 8 gates. Each active device has a gate.

I personally don’t think it matters too much which one you go with in terms of common centroiding however, there are other factors to consider. Like pelgroms law, larger devices match better so if you make the device too small by having a larger array, you might be better off with the smaller one. I personally use the first one a lot more than I use the second one.

Also, increasing the number of fingers tends to improve matching in planar CMOS, but especially so if you’re working with quantized devices like a vertical double gate device (FinFET).