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    How to fix a setup violation /hold violations in net-to-net path ??

    Hi,


    1.)why INPUT-to-OUTPUT path in sta is considered as a combinational path (not as both comb and seq) even though u see one launching flop and capture flop in between these ports ??

    2.)how this net-to-net setup/hold violations are fixed ??

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    Re: How to fix a setup violation /hold violations in net-to-net path ??

    paths are either IN-REG, REG-REG, REG-OUT. I don't understand what you have encountered.
    Really, I am not Sam.



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    Re: How to fix a setup violation /hold violations in net-to-net path ??

    Quote Originally Posted by ThisIsNotSam View Post
    paths are either IN-REG, REG-REG, REG-OUT. I don't understand what you have encountered.

    I am looking into STA theory. why you ignored IN-OUT path.?

    In the attached picture , I am talking about path-no 4 .

    And how to fix violations for the paths which is through a combinational logic like path no 4 ??



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    Re: How to fix a setup violation /hold violations in net-to-net path ??

    Quote Originally Posted by hcu View Post
    I am looking into STA theory. why you ignored IN-OUT path.?

    In the attached picture , I am talking about path-no 4 .

    And how to fix violations for the paths which is through a combinational logic like path no 4 ??
    Sure, you can have such paths in a toy example but they are useless... no meaningful modern circuit is not flopped.

    Either way, tools optimize them the same way as any other path. There's nothing special about them.
    Really, I am not Sam.



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    Re: How to fix a setup violation /hold violations in net-to-net path ??

    Quote Originally Posted by ThisIsNotSam View Post
    Sure, you can have such paths in a toy example but they are useless... no meaningful modern circuit is not flopped.

    Either way, tools optimize them the same way as any other path. There's nothing special about them.
    Have you not seen any "net to net " timing path violations in the timing reports.?



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    Re: How to fix a setup violation /hold violations in net-to-net path ??

    Quote Originally Posted by hcu View Post
    Have you not seen any "net to net " timing path violations in the timing reports.?
    what timing reports?
    Really, I am not Sam.



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    Re: How to fix a setup violation /hold violations in net-to-net path ??

    the .rpt file that comes after the command "report timing -num_paths 3000 > timing.rpt" during synthesis. From the textbooks what i came to know is, net-to-net violations is addressed using "set_input_delay" constraint. Is that true ??



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  8. #8
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    Re: How to fix a setup violation /hold violations in net-to-net path ??

    Quote Originally Posted by hcu View Post
    the .rpt file that comes after the command "report timing -num_paths 3000 > timing.rpt" during synthesis. From the textbooks what i came to know is, net-to-net violations is addressed using "set_input_delay" constraint. Is that true ??
    set_input_delay is used to set the input delay of an input with respect to a clock. but the path type you are referring to is not sequential. I don't see how it can help.
    Really, I am not Sam.



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    Re: How to fix a setup violation /hold violations in net-to-net path ??

    the question posed to me is, how to fix setup violation ? my answer is to reduce the combinational path delay sitting in between Lflop and Cflop.
    the next question is, how you do that ? my answer is, By registering the data available at certain point in the combinational logic.

    the next question is, Then how you address this, if it is a pure combinational block.? while im thinking, she said, have you not seen any net-to-net timing path in your reports ?

    Then i thought that , discussion went from reg2reg portion to port-to-port .

    I presented everything i encountered. I want some light on this. I am confused what she was trying to get from me ??



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    Re: How to fix a setup violation /hold violations in net-to-net path ??

    Quote Originally Posted by hcu View Post
    the question posed to me is, how to fix setup violation ? my answer is to reduce the combinational path delay sitting in between Lflop and Cflop.
    the next question is, how you do that ? my answer is, By registering the data available at certain point in the combinational logic.

    the next question is, Then how you address this, if it is a pure combinational block.? while im thinking, she said, have you not seen any net-to-net timing path in your reports ?

    Then i thought that , discussion went from reg2reg portion to port-to-port .

    I presented everything i encountered. I want some light on this. I am confused what she was trying to get from me ??
    I think the answer she was looking for was 'buffering'.
    Really, I am not Sam.



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