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  1. #1
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    Aspect ratio for transistors in the matched layout array

    Dear friends,

    In my layout design I can change the aspect ratio (W/L) for the unit cell transistor in the matched MOS array. I can decrease it by increasing the array order or by increasing the number of fingers in the transistors.

    My first question,

    1. why I always see people talking about reducing the aspect ratio to make it square for the unit cell ? I am using channel length of 1 um.

    2. The second question what is the lowest practical limit of the aspect ratio in the matched array, is it possible to have aspect ration less than one (like 2um / 4 um) ?

    3. Third question is inverse to the second one, what is the maximum practical value of the aspect ratio ?

    4. The last but not the lease, what is better, reducing the aspect ratio by increasing the array order or by increasing the number of fingers ? of course mixing of both is possible.

    Sorry to ask multiple question but I am trying to avoid similar topic post

    Thank you very much

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  2. #2
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    Re: Aspect ratio for transistors in the matched layout array

    Basically, you should always put dummy devices on the side, few of them, when matching is a concern. Then, aspect ratio shouldn't really matter much. However, every technology has a minimum W that's allowed. Then for a given L, this will define the lowest aspect ratio. I don't have the impression that people really prefer to have square aspect ratios. I think you should have large enough W that you can fit at least couple of contacts. As for the max aspect ratio, increasing W too much will have higher gate resistance, if you care about it.


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    Re: Aspect ratio for transistors in the matched layout array

    Dear Suta,

    Thank you for your reply,

    My lowest possible W is 0.4 uM and I am using L = 1 uM. It means it is no problem when I devide my transistor for the matching purpose in the array to have a unit size transistor of < 1 (like for example 0.4 uM / 1 uM).

    regardign the dummies, their affect on the matching will be visible only after fabrication right ??, more specific for etching process

    Thank you



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    Re: Aspect ratio for transistors in the matched layout array

    I don't understand why you want to use min width for your transistors in the array.

    Dummies are for matching and of course their effect will be visible after fabrication. In schematic they are just another shorted device. But if you do extraction of the layout which includes all layout effects, then you will be able to see the effect of the dummies on matching


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    Re: Aspect ratio for transistors in the matched layout array

    Dear Suta,

    It is clear that small transistor get worse effect during the etching process and I am not intending to minimize my transistors unit cell in the array to be very small. but I am forced to do because my differential pair for example using small transistors (10 uM/ 1 uM).

    my array pattern is ABBA/BAAB. it means now every trnsistor is divided by 4 so the unit cell transistor size is 2.5 uM.
    Add to this if I want to use even number of gates per unit cell to reduce the number of drains and getting better behavioural, so if I use two gate per cell the actual size will be 1.25 uM/1 uM.

    Thank you very much



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