Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Analog Design System(ADS) verilog_a_Tutorial_PSFETCV error

Status
Not open for further replies.

yyy963741tw

Newbie level 4
Joined
May 22, 2019
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
35
error.png
I simulated the example of veriloga tutorial workshop
but with error message that :
Error detected by hpeesofsim during netlist flattening.
`psfetv1' is an instance of an undefined model `psfetv'.
How can i solve it?
 

ADS is not an Analog Design System.
It is an Advanced Design System.

Show me netlist.

Simply you don’t include model definition which is described by Verilog-A or ADSsim language.
 
Last edited:

netlist.png
I am sorry to mistype the word.
how could i inculde th e model
this tutorial example workspace should not already fininshed?
 


so i should copy the veriloga code into netlist?


I mean this work provided by program tutorial . It Should be able to simulate normally . But it can't
 

Check the schematic in your tutorial. It seems that you missed to add some model/library include block which tells ADS about the model details.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top