sushl
Junior Member level 2
Hi all ,
I've tried a simple EXOR verilog code along with test bench on the EDA playground, test bench is forced with inputs 00,01,10,11 respectively ;
can anybody tell me why were not getting correct outputs? all are showing x,x,x,x in the LOG.
Here's the link to page
https://www.edaplayground.com/x/3QTX
thanks and regards
Sushl
I've tried a simple EXOR verilog code along with test bench on the EDA playground, test bench is forced with inputs 00,01,10,11 respectively ;
can anybody tell me why were not getting correct outputs? all are showing x,x,x,x in the LOG.
Here's the link to page
https://www.edaplayground.com/x/3QTX
thanks and regards
Sushl