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  1. #1
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    Innovus changing pin connections

    Hi!

    Today I encoutered a problem when porting a digital block design from innovus to virtuoso:

    I extracted the netlist from Innovus with save netlist aswell as the DEF and imported them to virtuoso.
    During LVS in virtuoso I discovered that all of the Flip-Flops with reset (the synthesis tool seems to take them in around 10% of the cases a FF is needed, I guess because of the timing), don't have their reset pin connected (the design is pipelined and needs to be flushed anyway) and should be connected to vdd.
    So I checked the netlist generated during synthesis (cadence genus) and there the pin should be connected to 1'b1. The netlist I extracted from Innolvus after timing signoff, also has it tied to 1'b1.
    But when I look into the design browser of innovus, the pins are connected to 0x0. But it seems that doesnt mean it should be connected to VSS....
    I think I could solve all of this by redoing my design with a reset and tying it to vdd externally, but I think this behaviour is very strange, especially because the extracted verilog netlist shows the connections while in innovus design browser they are not there.

    Thank you for your help!

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  2. #2
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    Re: Innovus changing pin connections

    you need to learn about tiehigh tielow cells. no signal pin of a digital cell should be connected to VDD/GND directly.
    Really, I am not Sam.



  3. #3
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    Re: Innovus changing pin connections

    Thanks for that input!
    At what point of the workflow do I add them? after CTS before doing routing with nanoroute?

    Just as a side question: is there any reason to use regular filler cells over decap fillers?



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  4. #4
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    Re: Innovus changing pin connections

    you can add tie cells as early as logic synthesis.

    decap cells leak because they have transistors, filler cells don't always have transistors in them. but you gotta check the specifics of the cells you have for the technology you are working with.
    Really, I am not Sam.



  5. #5
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    Re: Innovus changing pin connections

    Thank you again! For the filler cells I calculated the leakage and it is definitly doable for my current design.
    The only problem I have now is that I get DRC errors during LVS (not during DRC). It says unstable device fpr pdiode_DIODE_105. It has the error both at the diffusion area of the LOGIC1 cell (it contains a resistor and a diode) and also at a NO3L cell where there isn't even a diode (Error is shown also at a diffusion area, see https://imgur.com/a/k7GE4at).
    Maybe you have an idea, since I searched the DRC files provided by xfab (I am working with XO35) and haven't found anything about diodes or unstable devices.

    Greetings,
    Alex



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  6. #6
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    Re: Innovus changing pin connections

    Quote Originally Posted by Alexxk View Post
    Thank you again! For the filler cells I calculated the leakage and it is definitly doable for my current design.
    The only problem I have now is that I get DRC errors during LVS (not during DRC). It says unstable device fpr pdiode_DIODE_105. It has the error both at the diffusion area of the LOGIC1 cell (it contains a resistor and a diode) and also at a NO3L cell where there isn't even a diode (Error is shown also at a diffusion area, see https://imgur.com/a/k7GE4at).
    Maybe you have an idea, since I searched the DRC files provided by xfab (I am working with XO35) and haven't found anything about diodes or unstable devices.

    Greetings,
    Alex
    Sorry I cannot find an EDIT button:
    I was able to solve the problem by adding some more diffusion area. No idea why this error occoured!



  7. #7
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    Re: Innovus changing pin connections

    no idea either
    Really, I am not Sam.



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