# Class AB output stage for VDD=1.8V

1. ## Class AB output stage for VDD=1.8V

Hello

I am considering using the topology shown in "A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries" for implementing a class AB output stage.

It is stated several places that this topology is suited only for moderately low voltages as the supply voltage is limited by two diode voltages and one vdsat over M20 and M19 in the picture. I guess this depends on the technology used.

I am using a technology with VDD=1.8V and Vtn around 500mV and Vtp around 600mV. I am able to size the transistors, so that all transistors are in saturation when there is no load on the output. When a load is applied, M19 and M20 quickly falls out of saturation. Is this due to the limited voltage margin I have? What condition sets the maximum allowed current draw in this type of circuit?

Is it possible to make this topology work with VDD=1.8V or should I go for another variant?

Thanks.

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2. ## Re: Class AB output stage for VDD=1.8V

It is normal for the current in the mesh M19/M20 to shift mostly into the NMOS or the PMOS side of the mesh depending on the amount and direction of the output current. That means one side of the mesh will have to go in almost cut-off, while the other takes all the current as it may shift from saturation into triode.

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3. ## Re: Class AB output stage for VDD=1.8V

I see.

That is what i am observing.

If I connect a current source at the output to start sinking current, the PMOS will start to deliver current to the output.
I understand the circuit as that the gate drive will then start to decrease for the NMOS and increase for the PMOS.
What I now see, is that when the node driving the NMOS gate falls below a certain level as it start to shut off, M16 and M18 falls out of saturation. This occurs for a common-mode input voltage of around 1.5V, as it seems to avoiding me having rail-to-rail output operation. I would like this to occur for common-mode inputs closer to the rail I think. Is there any tips you can give me in order to achieve this? Any dimensions I should be looking into to tweak?

-Thanks.

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4. ## Re: Class AB output stage for VDD=1.8V

Now I understand.

I was was pushing the output transistors out of saturation and therefore the collapse of voltages in the summation stage.

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