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VHDL code for 74hc4094

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sa007jbond

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I am looking for a VHDL code for 74hc4094, for example as i have for 74HC595...


Code VHDL - [expand]
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LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
 
ENTITY C595 IS
    PORT( SRCK, SRCLRN, RCK, GN, SER: IN std_logic:='U';
          QA, QB, QC, QD, QE, QF, 
          QG, QH, QHH: OUT std_logic);
end C595;
 
ARCHITECTURE behav OF C595 IS
SIGNAL SO, Qstate : std_logic_vector(7 downto 0);
 
begin
   process(SRCK, SRCLRN) 
   begin 
      if SRCLRN='0' then 
         SO <= "00000000"; 
      elsif (SRCK'event and SRCK='1') then 
         SO(0) <= SER; SO(1) <= SO(0); SO(2) <= SO(1); SO(3) <= SO(2); 
         SO(4) <= SO(3); SO(5) <= SO(4); SO(6) <= SO(5); SO(7) <= SO(6);
      end if; 
   end process; 
 
   process
   begin 
     wait until (RCK'event and RCK='1');
     Qstate <= SO;
   end process; 
 
   QA <= Qstate(0) when GN='0' else 'Z';
   QB <= Qstate(1) when GN='0' else 'Z';
   QC <= Qstate(2) when GN='0' else 'Z';
   QD <= Qstate(3) when GN='0' else 'Z';
   QE <= Qstate(4) when GN='0' else 'Z';
   QF <= Qstate(5) when GN='0' else 'Z';
   QG <= Qstate(6) when GN='0' else 'Z';
   QH <= Qstate(7) when GN='0' else 'Z';
   QHH <= SO(7);
 
end behav;

 
Last edited by a moderator:

Hi, it's difficult to read a code when it's not in a code tag.

I looked up a datasheet for the IC by Nexperia and on page 4/19 Table 3 gives the functional description of the behaviour of the device. If you take some time and study the table and the timing diagram (Fig. 7) that follows, you should be able to write a behavioural VHDL code for it.

Just compare the code you have for the 74HC595 and the info in its datasheet and you'd be able to write one for the 74HC4094 .
 

See code....So basically
1. You shift data into SO.
2. Qstate is a snapshot of that.
3. Qstate is deconstructed into Qx parts.

Look for datasheet - see heading : 8-stage shift-and-store bus register.

You are given fig 4, that will help your behavioural model.
 

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