Including VHDL libraries to add two signals

Hi,

I have very basic question regarding VHDL libraries. I just want to add two 32 bit unsigned numbers. I need some help regarding which library I really need to include in the VHDL code

The libraries are here


and the signal in which I need to add a constant 32 bit unsigned number is here

Std_logic_arith and std_logic_unsigned are non-standard VHDL libraries. So I would recommend the use of only numeric_std, which is part of the VHDL standard.

ieee.numeric_std.all; -- This is the official source for "unsigned" and "signed" types. Just use this. Monkeys on a ladder and whatnot.
ieee.std_logic_arith.all -- This also defines "unsigned" and "signed" types. It wasn't from ieee, so people will look at its inclusion with murder-eyes.
ieee.std_logic_unsigned.all -- This is the controversy package. It is basically "use verilog". But it also wasn't from ieee so it also has the monkeys on a ladder issue. VHDL-2008 has an official version of this -- and this version should be used where applicable.

std_logic_unsigned/numeric_std_unsigned make VHDL more like Verilog. SLV's get an unsigned interpretation. This is an issue with equality comparisons. With SLU, "0100" = "100", but without SLU, "0100" /= "100".

I would use numeric_std only and an unsigned constant.

If I remove "use ieee.std_logic_arith.all;" then it's fine but I have to keep "use ieee.std_logic_unsigned.all;" together with "use ieee.numeric_std.all; " to have no errors in simulation.

If "use ieee.std_logic_unsigned.all;" is a non-standard VHDL, would it create any issue in synthesis ?

Here are the libraries which I have added in VHDL file.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

std_logic_unsigned gives std_logic_vector an unsigned interpretation. This is similar to Verilog. It works fine. The gotcha is that "0" = "00" now, while "0" /= "00" (+warning) before.

The issue is with + operator. If I remove "use ieee.std_logic_unsigned.all;" then it gives error in simulation. Therefore, I have to use both

use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

Is that ok to run synthesis with above two libraries ?

joniengr said:

The issue is with + operator. If I remove "use ieee.std_logic_unsigned.all;" then it gives error in simulation. Therefore, I have to use both

use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

Is that ok to run synthesis with above two libraries ?

Click to expand...

Yes. It seems weird, but this works fine. std_logic_unsigned defines functions on std_logic_vector. There are no conflicts with numeric_std.

joniengr said:

The issue is with + operator. If I remove "use ieee.std_logic_unsigned.all;" then it gives error in simulation. Therefore, I have to use both

use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

Is that ok to run synthesis with above two libraries ?

Click to expand...

Yes, it's okay to use it. No issues at all.