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How to map 2 inputs to an input between 2 components?

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potatovdhl

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Not even sure if my title describes it correctly.

I'm trying to instantiate 2 components together, in this case a register file and an ALU

In the instantiation entity, i have

Code:
 PORT(
      ....
      inputdatapath: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      ....
      )

in the RF component i have an 8 bit input and in the ALU component i have an 8 bit output

I wanted to wire the ALU output into the 8 bit input of the RF with a signal, while also having the RF input be mapped to the inputdatapath. Basically 2 inputs into the RF input.

I seem to keep getting positional association errors because i'm doing it wrong.

datapath.png

Not sure what i should do to map something like this.

Thanks
 

Your drawing is shorting two drivers the inputdatapath "driver" and the output of the ALU. Having multiple drivers on a signal or into a component is not allowed. You need to use a multiplexer or show us the entire code so we can determine what you are trying to do.
 

Hi,

You need to have a signal that selects which data you want to transfer to the RF at any point in time. A single bit signal will do such that when that signal is '1' you select one of the data (ie either inputdatapath or ALU output) and when it is '0' you select the other.

It's easy to implement it with an IF/ELSE statement.
 

using a mux makes sense, the RF has extra selectors and enables to determine where the input goes so i thought omitting a mux was possible if they were simply connected together and giving it signals to enable a particular register would be enough.

thanks
 

using a mux makes sense, the RF has extra selectors and enables to determine where the input goes...

Of course. And for instance in VHDL, Post #3 would implement a mux.
 

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