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H-bridge current spike

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fsilva.cor

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Hi,
I'm simulating the following a class D amplifier as shown in the image. The PWM driving scheme is bipolar (25 kHz), the load is 20mH+1.9R, the driving resistors and the dead time (250ns) correspond to those of the gate driver I choose.
Untitled.png
The actual transistor I'll be using is the CSD18540Q5B, but as there is no open spice model of it, I'm simulating with the IPB090N06N3 which seems to be similar.

The problem I find is that simulation shows a current spike on the lower transistor each time it turn on. Do you know where might it come from?
Untitled2.png

Thanks,
Federico
 

Please show a few more simulations:
the gate drives for all 4 FETs (i.e. GS voltage)
the drain currents of all 4 FETs
 

Hi,
thanks for the quick response.
Here are some images of the simulations.
Untitled3.png
Untitled4.png

Regards
 

Why not post the zipped *.asc file so everyone can check the results on his own?
 

As suggested, I attach the .asc file.

Thanks
 

Attachments

  • HBridge.zip
    2.3 KB · Views: 70

At first sight, it's just Cds charging current. Increase the Rgchx gate resistors if you worry about the peak current.
 

Thanks, that does reduce the spikes, but it also reduces the system efficiency. Moreover, I'm trying to increase the switching frequency to 100 kHz in order to reduce the filter, but I can't get it to more than 83%. What do you you suggest I do?

Regards
 

you might consider putting in a resistive load on the sim ...

- - - Updated - - -

the sim might be giving the reverse recovery in the other fet - hence the current spike - ignore for now ...
 

Hi,

Understood. However, now I have the following questions:
1) Why do you say I may ignore reverse current for now? Is it overestimated by the simulation?
2) How can you say the current due to Cds is 4.5 A?
3) How could I improve efficiency?

Many thanks
 

You are right, it's mostly reverse recovery current. Peak current of open half bridge (Cds related) is only 4.5 A.

- - - Updated - - -

As said, operating the half bridge without load connection gives the Cds related switching current.

Don't know if the model is accurate, but reverse recovery is probably not overestimated. Easy peasy is assuming that the real application involves a real load and less reactive current. If that's not the case, you might look for transistors with faster body diode.
 
not Cds, reverse recovery of internal diode - if you dissect the fet model you may see it there ... - in real world it will likely be less for the Rgate used
 

I understand that is unavoidable. However, my interest is in efficiency, as the system will be battery powered. How can I improve it?
 

you seem not quite to understand the full import of the word - unavoidable. Your sim and the real world will be different, choose mosfets with fast anti-parallel diodes ( they are an intrinsic part of the fet )
 
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