Substrate contact vialation

Hi Team
I am using TSMC 65nm 0V－1.2V technology to tape out an IC. I created a filler cell with substrate contact as this.

1. Create a unit filler cell with a unit layout connect M1,3,5,7 to gnd and M2,4,6 to vdd
2. Add substrate contact form M1 to gnd.(I heard there is no such thing as too much substrate contact)
3. Fill the opening in your layout with this small unit filler.

So all my psub is connected to a good gnd. However, when I added the TSMC ESD devices, there is an error in LVS.

WARNING: Stamping conflict in SCONNECT - Multiple source nets stamp one target net.

I suspect it is due to the substrate connect (error will disappear when I remove the substract contact). The ESD device has it's own substrate contact connected the psub at a different voltage then gnd....Therefore in my layout, the sub is connected to 2 different voltage pin through substrate contact.

Can anyone have any idea how to solve this problem?
Thanks Allen

Updates:
I think it is the LVS model file problem. Does anyone have used TSMC 65nm slim I/O and it's LVS model files? What have you included to test LVS?

Update： I verified that when I place a DCUP cell (DC decoupling cell made of mos capacitor provided by TSMC) on my layout view, the mos capacitor is automatically connected from "VDD" to "VSS", But for the analog I/O, the pin to the core circuity is called "VDD" and "AVSS". This is discrepancy caused the LVS error, Can anyone please teach me how to fix it by making the DCUP cell connect to "analog VSS"?

- - - Updated - - -

For TSMC digital I/O, the pin to the core are VDD and VSS. So no error is reported by LVS. However, for analog I/O the pin to the cores are VDD and AVSS, LVS seems very confused with this. Do you think if I change the LVS netlist of ESD makes any sense? In other words, Is there any problem if I connect the substrate to AVSS instead of VSS?

How do you do connections on the top level ? If these ground signals are supposed to be same, and connected on the top, then there should be only one signal name ( one pin !)
However be careful, if AVSS is supposed to be an "isolated ground", in this case you should use guard-ring.

If one gives two different names for the same signal ( ground in this case), obviously LVS won't like it.

I suggest you look at what a typical filler cell looks like. It is not supposed to use higher metal layers.