+ Post New Thread
Results 1 to 11 of 11
  1. #1
    Member level 5
    Points: 1,162, Level: 7

    Join Date
    Jun 2015
    Posts
    83
    Helped
    0 / 0
    Points
    1,162
    Level
    7

    VHDL modulo 2^64 addition

    I'm working on SHA-512 VHDL implementation and i need to perform (addition mod 2^64)

    How can i make the following addition as (modulo 2^64 addition)

    Code:
      a(i)          <= std_logic_vector(unsigned(h(i-1)) +unsigned(f3(i)) + unsigned(f0(i)) +unsigned(k(i)) + unsigned(w(i))  + unsigned(f2(i)) + unsigned(f1(i)));

    •   AltAdvertisement

        
       

  2. #2
    Advanced Member level 4
    Points: 6,093, Level: 18

    Join Date
    Feb 2015
    Posts
    1,000
    Helped
    284 / 284
    Points
    6,093
    Level
    18

    Re: VHDL modulo 2^64 addition

    make a(i) 64 bits.


    1 members found this post helpful.

  3. #3
    Member level 5
    Points: 1,162, Level: 7

    Join Date
    Jun 2015
    Posts
    83
    Helped
    0 / 0
    Points
    1,162
    Level
    7

    Re: VHDL modulo 2^64 addition

    Quote Originally Posted by vGoodtimes View Post
    make a(i) 64 bits.
    All inputs and output are already 64-bit.
    but this equation gives wrong result



    •   AltAdvertisement

        
       

  4. #4
    Advanced Member level 1
    Points: 2,489, Level: 11

    Join Date
    Aug 2016
    Posts
    440
    Helped
    69 / 69
    Points
    2,489
    Level
    11

    Re: VHDL modulo 2^64 addition

    Hi,
    I noticed that you used this: std_logic_vector(unsigned(h(i-1))

    Why not try this: std_logic_vector(unsigned(h(i)-1)

    I don't quite understand what you're doing though but if you show your code, then I can follow.
    -------------
    --Akanimo.


    1 members found this post helpful.

  5. #5
    Super Moderator
    Points: 75,476, Level: 67
    Achievements:
    7 years registered
    Awards:
    Most Frequent Poster 3rd Helpful Member

    Join Date
    Apr 2014
    Posts
    15,299
    Helped
    3485 / 3485
    Points
    75,476
    Level
    67

    Re: VHDL modulo 2^64 addition

    Hi,

    Signed or unsigned values?

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



    •   AltAdvertisement

        
       

  6. #6
    Advanced Member level 4
    Points: 6,093, Level: 18

    Join Date
    Feb 2015
    Posts
    1,000
    Helped
    284 / 284
    Points
    6,093
    Level
    18

    Re: VHDL modulo 2^64 addition

    Quote Originally Posted by MSAKARIM View Post
    All inputs and output are already 64-bit.
    but this equation gives wrong result
    please give an example of inputs-outputs giving a wrong value.


    1 members found this post helpful.

  7. #7
    Advanced Member level 4
    Points: 6,072, Level: 18
    kripacharya's Avatar
    Join Date
    Dec 2012
    Location
    New Delhi
    Posts
    1,166
    Helped
    179 / 179
    Points
    6,072
    Level
    18

    Re: VHDL modulo 2^64 addition

    Quote Originally Posted by KlausST View Post
    Hi,

    Signed or unsigned values?

    Klaus
    Since every quantity in the equation is specified as unsigned, then surely it's unsigned ?

    Also, I did not understand the symbol " <= ". Is this a qualifier equation or is it an inequality ??



  8. #8
    Super Moderator
    Points: 75,476, Level: 67
    Achievements:
    7 years registered
    Awards:
    Most Frequent Poster 3rd Helpful Member

    Join Date
    Apr 2014
    Posts
    15,299
    Helped
    3485 / 3485
    Points
    75,476
    Level
    67

    Re: VHDL modulo 2^64 addition

    Hi,

    Since every quantity in the equation is specified as unsigned, then surely it's unsigned ?
    For sure you are right. ... I should have been more concentrated when reading post#1.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



    •   AltAdvertisement

        
       

  9. #9
    Super Moderator
    Points: 257,269, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    44,887
    Helped
    13656 / 13656
    Points
    257,269
    Level
    100

    Re: VHDL modulo 2^64 addition

    Also, I did not understand the symbol " <= ". Is this a qualifier equation or is it an inequality ??
    VHDL signal assignment.


    1 members found this post helpful.

  10. #10
    Member level 5
    Points: 1,162, Level: 7

    Join Date
    Jun 2015
    Posts
    83
    Helped
    0 / 0
    Points
    1,162
    Level
    7

    Re: VHDL modulo 2^64 addition

    Quote Originally Posted by Akanimo View Post
    Hi,
    I noticed that you used this: std_logic_vector(unsigned(h(i-1))

    Why not try this: std_logic_vector(unsigned(h(i)-1)

    I don't quite understand what you're doing though but if you show your code, then I can follow.
    h(i-1) is a previous iteration for h ( NOT h(i)-1 )



  11. #11
    Advanced Member level 4
    Points: 6,093, Level: 18

    Join Date
    Feb 2015
    Posts
    1,000
    Helped
    284 / 284
    Points
    6,093
    Level
    18

    Re: VHDL modulo 2^64 addition

    The code shown looks correct for this problem. My guess is that one or more of the terms is incorrect.

    For any encryption core, you really need to get detailed test vectors. Not just input and final output, but all intermediate terms for every iteration. when everything looks random by design it is harder to intuitively trace the problem to a source.



--[[ ]]--