Opamp Design Procedure,

Hi, I am new to opamp design field. Currently I want to design a two stage cascode opamp in 65 nm process, and I have two questions:

1) Is there any reference that guides step by step design procedure? specially a design guide on CMFB circuits?
2) How can I change the drain source voltages of the transistors in my design?

Thanks a lot

Hi,
Your 2nd question tells you are at the very beginning of analog IC design, however the 1st question is far from it.
So I think these are the correct steps for you:
a, understand how a MOS device operates from a good book, the transfer+output characteristics (book: Behzad Razavi - Design of analog CMOS integrated circuits)
b, learn basic circuit building blocks, CS and CD amplifier stages, differential and cascode amplifier (book: same from B.Razavi)
c, design the simpliest 2 stage OpAmp, which you will extend to a folded cascode OPAmp later (P.E.Allen lessons, google for them, there are a lot of great pdf from he)
d, change single-ended OPAmp to a differential one (book: Gray/Hurst/Lewis/Meyer - Analysis and Design of Analog Integrated Circuits, contains a lot of explaination about CMFB)

Thank you frankrose,

I know that the second question seems silly, but the problem is that in nm processes, the drain source voltage somehow becomes a headache. I was asking if someone knows a particular solution for forcing a transistor to operate in saturation. In addition to that, I know the basics of operation of CMFB and I am familiar with basic structures but I wanted to see if there is any special resource for design and simulation of CMFB circuit. All the references that I have reached explain the basics of operation but no one is talking about transistor dimension choice or other specifications.

There is no silly question, just be more accurate please. If you are familiar with stuffs what is this headache with the drain-source voltage? In general a simple diode-connected device force the transitor to operate in saturation, 65nm shouldn't matter, and this is probably not a useful information for you.
It would be better to discuss about your unique case, where you have an issue, which transistor not saturates, show a schematic with annotated voltages for example with the headache.

And choice of device sizes is a complex question, depends on what you want, what is available. For example you obviously don't want big area with big costs, but some is required, because you have a minimal width+length too, and maybe even more area is necessary for matching, for load drive capability, or for noise reduction, but you want much smaller area to reach the target, then you have to find other circuit structure and/or you have to reduce an other parameter, like bandwidth, or you have to increase the consumption....for example. It is too complicated, references give a basic explaination for more parameters separately, but because these are multivariable systems noone can or wants to give an ultimate solution. That simply wouldn't work. And You, the designer has to give the specifications.

Almost any deep submicron process will have a
second set of "I/O" transistors with thicker gate
oxide and higher min channel lengths. If you want
more dynamic range this is what to use.

There's a ton of CMOS fully differential op amp
papers in the red rag (JSSC) but you may need to
go back a decade or more to find them, back
when it was new enough art to be worth publishing.
I'm sure there are many theses out there as well.

Later versions of Gray & Meyer, when they moved
from bipolar to CMOS emphasis, might be worth
looking at. archive.org has many textbooks you can
check out and download for free.