# Is this old design a candidate for CPLD?

1. ## Is this old design a candidate for CPLD?

Hi All,

I've got a design that uses a lot of discrete logic IC's to monitor/capture 64 transient digital logic levels. The 64 logic levels are normally high, and I want to detect if any of them go low in a certain period of time. This data is then logged by a microcontroller. Currently, each logic level input goes to a flip-flop (32 total 74HC107), and then the flip-flop outputs get connected to parallel-to-serial shift registers (12 total 74HC165) in order to collect the data with a microcontroller. After the data is read, the flip-flops are reset for the next monitoring period.

I'd like to replace the discrete logic as it's becoming hard to source. At the same time I'd like to reduce my overall component count. So, I assume this design is a good candidate for CPLD?

Assuming that is correct, how do I estimate the size of the CPLD that I'll need to perform this task? Is it just about available I/O? What about required macrocells? Are flip-flops and shift registers macrocell intensive?

I'd like to select a device and start prototyping something so that I can eventually move in this direction, but at the moment I'm a complete newbie with programmable logic.

Any tips or words of wisdom?

Thanks,

John

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2. ## Re: Is this old design a candidate for CPLD?

You can do a simulation before you buy anything. Get Intel/Altera Quartus Prime (it's for free), you can build a logic circuit using block diagram a 74-family "virtual chips" and then compile it for different CPLDs and see if your design will fit into chips. You can start from Altera EPM3064 but it is 3.3V only.

3. ## Re: Is this old design a candidate for CPLD?

Hi,

So you want to check the logic state of 64 signal lines..
Hopefully they are already purely digital and don't need individual schmitt-triggers.

Now if you want individual flip flops, then this means you need 64 macrocells. One macrocell per flip flop.
Plus a macrocell for every counter bit. (Which is a flip flop)
Plus a macrocell for every output.
Plus let's say 20% .. 30% for additional logic and routing.

So the suggested 3064 will be too small.
Better try a 128 MC PLD.

Klaus

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4. ## Re: Is this old design a candidate for CPLD?

clearly you need 64 inputs

it isn't quite clear how many lines go to the microprocessor, but you can add that to the 64 inputs.

add at least 10% more free I/O pins
(tie some of the extra I/O pins to a plated through hole or equivalent, so you can add a wire for easy changes)

whatever device you use, even if you only use 10% of its available logic, it will take less board space,
cost less (cost of buying parts is only part of it - there's also hidden stock costs, kiting costs, receiving and QC, etc)
and if you get an in circuit programmable, (JTAG or something newer) you can fix it or upgrade it without a new design.

5. ## Re: Is this old design a candidate for CPLD?

Originally Posted by ezflyr
The 64 logic levels are normally high, and I want to detect if any of them go low in a certain period of time.
You're probably familiar with this grid arrangement, similar to the way a keyboard is scanned. The demo below has 9 sources. Each source has two diodes which steer the signal to a 3x3 grid. As soon as you detect one wire change state, start reading its data.

LED's indicate which source is active. (The first source is active).
To read 64 sources you need an 8x8 grid and 128 diodes. Orient diodes and supply rails to suit your purpose.

Your description implies only one source transmits at a time, nevertheless you can accept data from two sources simultaneously, since they can never have all the same output wires in common.

6. ## Re: Is this old design a candidate for CPLD?

Note that 'CPLD's don't really exist anymore or are very old if they do.

I'd look at Lattice MachXO and maybe Altera Max10 as the two main modern low end FPGA's (with built in flash that makes them 'look' like CPLD's). Lattice is probably the cheaper option but their tools are worse.

As said, download the tools and try your design. You can probably get by with the very lowest end parts. Note that this will add a programming step to your manufacturing process.

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7. ## Re: Is this old design a candidate for CPLD?

Hi,

Note that 'CPLD's don't really exist anymore or are very old if they do.
XILINX still calls some of their devices "CPLDs"
https://www.xilinx.com/products/sili...ices/cpld.html

Klaus

8. ## Re: Is this old design a candidate for CPLD?

Yeah but they're ancient and they've been steadily going obsolete.

Maybe some of them have assurance for future availability? I'd definitely check before using them.

But also are they cheaper than low end MachXO's?

EDIT: To answer my own questions yes, they do go cheaper than the FPGA's I suggested and I see end of lifes 5 years out. So I revise my suggestions somewhat. Seems reasonable to use if it works.

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