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    verilog ams simulation

    Hi. I have been trying to simulate verilog ams with components coded in verilog, veriloga and analog (pdk given mos).

    I have done it and can see the wave forms but there is a problem, the or gate coded in verilog doesn't switch in output waveform window. rest all other gates are fine. Click image for larger version. 

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    the third waveform is supposed to be or of 1st and 2nd but it is not okay.

    the peak voltage of pulse waveform which are inputs to verilog or is .85 V. is there any voltage above which only switching will occur?

    I had previously done the same for not gate and it was working fine for 0.85 Volts too.
    Or gate verilog code is fine and have verified it using test bench. What would be the possible reason for the wrong result.

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    Re: verilog ams simulation

    Quote Originally Posted by vicky2904 View Post
    I had previously done the same for not gate
    and it was working fine for 0.85 Volts too.
    Or gate verilog code is fine and have verified it using test bench.
    I can not understand what you want to mean at all.
    Describe grammatically correctly.

    Confirm AtoD and DtoA interface elements.



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    Re: verilog ams simulation

    I simply meant that if I generate symbol for a verilog code for not gate, it works fine. But when I try the same for or gate, waveforms at output do not switch. The first and second waveform in image in question is input to verilog or and third waveform is output which clearly doesnt react to input chages.

    I am using connectlib full fast 18v for interfacing.



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    Re: verilog ams simulation

    Quote Originally Posted by vicky2904 View Post
    I simply meant that if I generate symbol for a verilog code for not gate, it works fine.
    What do you want to mean by “generate symbol” ?

    Do you want to mean generating netlist from symbol ?

    What description do you use for not-gate and or-gate ?
    gate level HDL(Verilog-D) ?
    Verilog-A description ?
    Spice description ?



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    Re: verilog ams simulation

    What program do you use to simulate VerilogA?



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    Re: verilog ams simulation

    Quote Originally Posted by yyy963741tw View Post
    What program do you use to simulate VerilogA?
    Post processing tool is Cadence Simvision.
    So simulator is Cadence NCSim with AMS option which is named as AMS designer.



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