I/O supply and usage

Hi
I am trying to tapeout a mixed signal circuit using TSMC 65nm pdk. I need to input/output analog signals, sampled (analog) signals, DC signals, clock signals. The operating freq is in the proximity of 1GHz. Can I ask a few questions, please?

1. Can I just use analog I/Os for all the signals listed above, including clock signals? My reasoning is that the digital I/O is relatively slow and there is no need for me to transform my signal from 1.2V to 3.3V. On the other hand, there is no harm to use analog I/O for clock signal output.

2.There are 2 types of analog power cells to provide VDD from TSMC I/O lib. the power bus names are TAVDD and TACVDD. TAVDD is for analog domain supplied by the I/O voltage, whereas TACVDD is for analog domain supplied by the core voltage. To my understanding, these should be the supply voltage of the I/O. But that are the difference?

3. The analog signal I/O demand a secondary ESD device. I am thinking of a simple resistor and 2 diode connected mosfets. Is there a rule of thumb for the sizing of resistor or w,l of the mosfets?

Thanks
Allen

Hi allen,
I am not familiar with TSMC 65nm PD, but with I/O circuits in general so my answer might or might not be heplful/

1 - Analog I/O IP should come with a documentation in the PDK, in which AC/DC switching characteristics, min and max operating voltage and frequency should be defined. If your application's requirements are in the range of what analog I/O supports, then you should be fine.
2- Analog I/Os have multiple supplies. These supplies are usually I/O operating voltage, an analog auxiliary voltage for all the analog biaising requirements (this voltage is not necesseraly equal to the I/O operating voltage), and a core voltage which can be same or different than core supply rail depending on the noise acceptance. Again, the I/O documentation should give you the information.

3 - You should perform an ESD simulation to validate ESD function w.r.t your ESD specifications. The secondary device are sometimes required for CDM protection.

Rgrds,

Hi Dr_kca
Thanks for your reply! That's definitely very helpful! Can I please trouble you for one more questions? I am experiencing I/O conflict.

https://www.edaboard.com/showthread.php?384248-Substrate-contact-vialation

Thanks a lot!
Allen