# Differential pair question

1. ## Differential pair question

so I was asked this question during an analog design interview and I got it wrong. The picture of the diff. pair is linked above. VG1 is at Vdd/2 while VG2 is swept from 0 to VDD. The question was to plot Vout and to talk about the operating modes of the M1 and M2.

So my answer would be that in the beginning when VG2 is zero, M2 would be in cutoff while M1 would in saturation. At this point Vout is at VDD. As VG2 is swept towards VDD, at VDD/2 both M1 and M2 are in saturation and current across them is equally half the tail current. I am not sure what Vout is at this point. I am guessing around VDD - |VSG3,4|

When VG2 is at VDD, M1 is in cutoff with M2 being triode, Vout goes to a very low value.
so as VG2 is swept from 0 to VDD, Vout decreases from VDD to a low value. M1 goes from saturation to cutoff while M2 goes from cutoff to saturation and then to triode. My question how do I determine how low Vout is pulled to when Vg2 is at VDD?

From simulation it seems to depend on the drain of M5? If the minimum value across it is Vov of 5, is there any relationship between this and VG1, VG2?

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2. ## Re: Differential pair question

reference Horowitz and Hill, second edition, page 101 etc
extrapolating to FETs from BJTs:

this is a differential amplifier with current mirror active load

M1 and M2 are the differential amplifier Vout = (big gain) * (VG1 - VG2)

the current mirror is M3 and M4 which provide a high impedance load

M5 provides a constant current (since the gate voltage is fixed) which provides for the common mode gain

Vout is the output which must go to a high impedance load, or the gain drops significantly

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3. ## Re: Differential pair question

What is important to realize here is that you have a pmos current mirror as a load which will always try to fix 1:1 current ratio in the two branches of the diff pair.

It is easy to figure out what will happen if the gate of M2 varies from 0 to Vdd/2. Almost all of the tail current will go through M1 since M2 is off. Since there is no current in M2 but through the PMOS mirror M4 wants to source current equal to Itail, there is no other way but for M4 to go in deep triode with Vds=0 and then Vout=Vdd.

When VG2=Vdd/2, the tail current splits equally in M1 and M2 and Vout is defined by the output resistance of M4 and M2 but will be somewhere in the middle.

Interesting is what happens when VG2 continues increasing beyond VDD/2. The drain of M1 is always one Vgs of M3 below Vdd, so M1 remains in saturation. And because of the PMOS mirror, the currents in the two branches of the diff pair will want to stay more or less equal to Itail/2. However, since the gate of M2 goes up, M2 will want to sink more current and thus drive Vout lower. At some point M2 goes in triode but the currents in the two branches continue to be mostly equal because unlike before, M4 is well into saturation and the PMOS mirror works fine. With M2 going into triode and deeper into it, Vout has no choice but become equal to the tail node (the common source point of M1 and M2) because the Vds of M2 tends towards 0. Even then the currents into the two diff pair branches remain equal. So, Vout is then limited on the lower side by the tail node, which in turn is defined by Vdd/2-VGS1 (M1 works as a source follower now with current equal to Itail/2). VGS1 is the result of Itail/2 going through M1.

All this is for the case when there is no extra load connected to the output of the diff pair as shown on the picture above.

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4. ## Re: Differential pair question

Originally Posted by sutapanaki
What is important to realize here is that you have a pmos current mirror as a load which will always try to fix 1:1 current ratio in the two branches of the diff pair.

It is easy to figure out what will happen if the gate of M2 varies from 0 to Vdd/2. Almost all of the tail current will go through M1 since M2 is off. Since there is no current in M2 but through the PMOS mirror M4 wants to source current equal to Itail, there is no other way but for M4 to go in deep triode with Vds=0 and then Vout=Vdd.

When VG2=Vdd/2, the tail current splits equally in M1 and M2 and Vout is defined by the output resistance of M4 and M2 but will be somewhere in the middle.

Interesting is what happens when VG2 continues increasing beyond VDD/2. The drain of M1 is always one Vgs of M3 below Vdd, so M1 remains in saturation. And because of the PMOS mirror, the currents in the two branches of the diff pair will want to stay more or less equal to Itail/2. However, since the gate of M2 goes up, M2 will want to sink more current and thus drive Vout lower. At some point M2 goes in triode but the currents in the two branches continue to be mostly equal because unlike before, M4 is well into saturation and the PMOS mirror works fine. With M2 going into triode and deeper into it, Vout has no choice but become equal to the tail node (the common source point of M1 and M2) because the Vds of M2 tends towards 0. Even then the currents into the two diff pair branches remain equal. So, Vout is then limited on the lower side by the tail node, which in turn is defined by Vdd/2-VGS1 (M1 works as a source follower now with current equal to Itail/2). VGS1 is the result of Itail/2 going through M1.

All this is for the case when there is no extra load connected to the output of the diff pair as shown on the picture above.

Hey sutapanaki, thanks for the detailed explanation. It helped a lot. I wasn't sure what happened to M1 as VG2 is increased gradually from VDD/2 to VDD. I see that now it continues to stay in saturation while M2 goes into triode because the of the increase of gate voltage. Vout is driven (or close) to the value at the tail node. The current through both continues to be Idd/2. I did a simulation in LTSpice and it showed the same. Thanks for your help.

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