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  1. #1
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    How to measure the gain of LDO in cadence

    Hey Team,
    I am designing the Low Voltage dropout regulator.
    My input voltage is 2V and the output required is 1.2V. I used a two-stage op-amp as my error amplifier.PMOS devise as pass element.
    I am measuring my gain between y and input as shown in my diagram providing ac signal at the input side. Is this the correct way to measure the gain in LDO?
    And by doing this I am getting very less gain so can anyone explain to me how to increase it? For my op-amp, the gain is 60dB.
    Thank you in advance


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  2. #2
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    Re: How to measure the gain of LDO in cadence

    Your input difference voltage is {vbg-vin1}, I would tap that
    with a vcvs to get a ground referred input difference voltage
    that's real-time-valid for all analyses. Use this as the gain
    denominator and the phase "zero reference".



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  3. #3
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    Re: How to measure the gain of LDO in cadence

    The annotated DC node voltage values(maybe not they are annotated?) are very bad, the PMOS passing device's gate voltage is almost 0V.
    1st solve that to control the PMOS with smaller |Vsg|. Otherwise it is not even an LDO. An enhanced resistive driver perhaps.
    "Try SCE to AUX." /John Aaron/



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