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PMOS input Folded Cascode 0.35µm

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melkord

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Hi,

I am designing this opamp with TSMC_SCN_2P3M 0.35µm tech.
So far I am trying to mix and match recipe from books and some threads in this forum.
But every step always give me some confusion because each equation has more than one unknown variables, unless I use some values from tables in the books.

I have some questions:
1. Which L should I use for my technology?
from here, for 0.18µm, the L used is 0.35µm.

2. which table should I use e.g. for VDS,sat, Vth, Von?
I am borrowing Baker 2ns ed. Table 9.1 p.292 and Table 9.2 p300 for long and short channel, respectively.
I am borrowing Gray as well.

3. Should I define Vbias-es first or W/L first?
I feel this is like a chicken and egg problem, lol.

I am aware that there have been so many thread discussing this topology but they are not exactly like mine.
If someone can point me where to look, I really appreciate it.

the spec:
Av0 = 90dB
Fugb = 12 MHz
SR = 10V/µs
PM = 70 deg
Vout,pp = 2.5V
Vsupply = +1.65v, -1.65v


folded_cascode.PNG
 

1. Which L should I use for my technology?
from here, for 0.18µm, the L used is 0.35µm.

For general analog design, the L used is typically 2-3 times the minimum length. This choice is a good trade-off between speed and gain.

2. which table should I use e.g. for VDS,sat, Vth, Von?
I am borrowing Baker 2ns ed. Table 9.1 p.292 and Table 9.2 p300 for long and short channel, respectively.
I am borrowing Gray as well.

If you read baker's book, there's a modeling procedure in obtaining the values listed in that table. Follow this procedure using your own technology (Note: the table is only a guide). Moreover, typical parameter values such as unCox, Vth, etc. are obtained from graphical analysis or the family of curves for a transistor.

3. Should I define Vbias-es first or W/L first?
I feel this is like a chicken and egg problem, lol.

What do you mean when you say Vbias? are they the input common mode? you have a current reference already, use it as basis and mirror those currents at each branch for the desired bias current. Normally in today's circuits, power budget is the primary concern so once you've determined how much the circuit should disippate then you can determine the bias currents at each branch (Itotal=P/V). From this you can determine which topology to use (i.e. I need high gain, high slew rate, then I'd like to try a coscoded amplifier with push-pull output to see if I reach my specs).

As a starting guide, In allen's book "CMOS Analog Circuit Design, 3rd ed." shows a popular design procedure for a 2 stage op-amp. (chapter 6).
 
It is a chicken and egg problem in many aspects, so don't disrepair You should expect ot go through few iteration until design is ready.

I looked at your schematic. The bias reference caught my attention. Are you sure it works? The two branches of the reference have the same size transistors for the PMOS, the NMOS and the pnp diodes. Which means you force the same current. But in the right branch you also have a resistor so the circuit symmetry wants to force 0V across resistor but it you don't want this. In fact, these self-biased circuits usually have at least two operating points, one of which is 0 and it may happily stay there with no current.

What length you should use - basically people use different lengths for different parts of the amplifier. Cascodes can be minimal L, i.e. 0.35 in your case. Input diff pair depends. If you want gain, you use bigger L. If you want speed, use smaller L. This of course trades off with other things. In your case since it is a folded cascode structure, the input transistors contribute to gain through their gm, not through their gds. So, it is OK to use smaller L there for faster design but it will trade maybe with matching and flicker noise if you care about it.

You don't use tables from books to design. You have your own technology, so you should use that technology's parameters.

Biases are consequence of the other parameters of the design. For example, you need certain UGBW. For your amplifier it is approx gm1/Cload. You can choose gm1 (gm of the diff pair) and Cload (maybe it is fixed for you from the thing the amp drives and then you know it). Once you have an idea what is the gm1 you can decide how much current you will need to achieve that gm based on the size of the devices (few iterations needed here). Biasing cascodes will be mainly governed by keeping the transistors at their sources in saturation and also you need to make sure that the non-dominant poles caused by the cascodes are far way (2-3x) compared to your UGBW, which will also affect both current and cascode sizes.

Finally, you iterate through few solutions until you get it right. This is analog design and there is rarely a closed form solution for all transistors.

You may also have a look at gm/Id methodology for designing analog circuits.
 
Last edited:
Thank you for your reply. Sorry for late response from my side because I need to take care other subjects.
I have recalculated the size of the transistors. I attached in this post.
I updated the schematic drawing with some node names for clarity.

with this sizing, all transistors are in saturation except for M6-M7 in cutoff, M8-M9 in triode, M10-M11 in triode.
All transistor which are in saturation take 70uA as expected from calculation, except the long tail transistor which takes double of that, 140uA.

For general analog design, the L used is typically 2-3 times the minimum length. This choice is a good trade-off between speed and gain.


What do you mean when you say Vbias? are they the input common mode? you have a current reference already, use it as basis and mirror those currents at each branch for the desired bias current. Normally in today's circuits, power budget is the primary concern so once you've determined how much the circuit should disippate then you can determine the bias currents at each branch (Itotal=P/V). From this you can determine which topology to use (i.e. I need high gain, high slew rate, then I'd like to try a coscoded amplifier with push-pull output to see if I reach my specs).

As a starting guide, In allen's book "CMOS Analog Circuit Design, 3rd ed." shows a popular design procedure for a 2 stage op-amp. (chapter 6).

I meant by Vbias-es are all those 4 Vbias in the schematic to bias the long tail transistor M5, M3-M4, M11-M10, and low voltage cascode current source M6-M9.
In order to make all transistor in saturation, should I change the biasing transistor size or the size of the transistor which are not in saturation?
from derivation of low voltage cascode current source, I got this: VSG7 - Vt9 <= Vbias2 <= VSG7 + Vt9 - VSG9. This formula is the guidance to chose Vbias2 so VDS9 not more than Vt1.


I looked at your schematic. The bias reference caught my attention. Are you sure it works?
I recalculated the size and yes, it works. see the picture in this post.
The BJT PNP2 Emitter area is 8x larger than that of PNP1.
both branch, left and right, have 70uA right now and all MOSFET are in saturation.

You don't use tables from books to design. You have your own technology, so you should use that technology's parameters.
I am not sure whether what I am doing is correct or not. But what I did was I simulated single MOSFET, both PMOS and NMOS, and see the uoCox from simulation result.
it helps me to predict the current and during sizing.

Biases are consequence of the other parameters of the design.
I am totally beginner in this so I would like to ask.
is it a misleading way of thinking if I consider all biasing transistors (the ones in the green box) as a merely voltage supply for other transistor which have more important function with regards to the spec?
if no, I think I can adjust the size to get the proper bias voltages for Vbias2,3, and 4. is that the correct way in designing this analog ic?
II am thinking that way because the MOSFET in the folded cascode part are not in saturation. I guess it is because incorrect biasing voltages.

I really appreciate any suggestion.


Capture.PNG
 

OK, from the schematic it looks like both PNPs are the same size, but if you say they are 1:8 in area, that's good.

Yes,simulating transistors to extract their parameters is a good approach. There are better ways, like the gm/Id methodology I mentioned in my previous post, but your way can be a starting point.

No, it is not the correct way to think about the biasing the way you suggest. Out of the transistors in the green box, only the ones biasing the gates of the cascodes - Mn17, Mp12 can be considered as providing voltage bias. Only those you can adjust in size to get the voltages you need. The rest are current biases i.e. current mirrors. They mirror current in their respective branches and you don't care what the voltage will be. You care about proper current mirroring to Mp5, Mn3,4, Mp14,16.

As for the transistors in the folded branches not being in saturation - are you simulating your schematic open loop or you have the feedback loop closed? If you don't have the loop closed then you can not expect to get the correct output and your output will be railed either high or low.

It will be helpful if you can show some of the operating point information on your schematic - like Vds, Vdsat, Id, gm.
 
There are better ways, like the gm/Id methodology I mentioned in my previous post, but your way can be a starting point.

Yes, I have heard about that and will take a look into it.


No, it is not the correct way to think about the biasing the way you suggest. Out of the transistors in the green box, only the ones biasing the gates of the cascodes - Mn17, Mp12 can be considered as providing voltage bias. Only those you can adjust in size to get the voltages you need. The rest are current biases i.e. current mirrors. They mirror current in their respective branches and you don't care what the voltage will be. You care about proper current mirroring to Mp5, Mn3,4, Mp14,16.

hmm...I thought I can change the current mirror MOSFETs' size as well to adjust the current.
ok, i will just accept it for now and just change the size of the diode-connected MOSFETs.

are you simulating your schematic open loop or you have the feedback loop closed?

open loop, the power supply is +1.65v and -1.65v. the input of the diff pair are grounded, 0v.
Actually, I was also planning to ask about the proper simulation method in this forum once I get the sizing correct (all MOSFETs are in saturation).


It will be helpful if you can show some of the operating point information on your schematic - like Vds, Vdsat, Id, gm.

I can only show either voltage or current or charge directly in schematic.
if I wanted to see other small signal parameter, I double click the MOSFET.
I posted in other subforum about this and am waiting for the approval.
I am using S-Edit, btw.

here is the schematic with the numbers near the terminal are their voltage.

Capture2.PNG

and this is if I want to see the other parameters.

small-signal.PNG
 

Looks like the gate voltage of Mn10/11 is lower than the source voltage which puts them in cut-off. You will need to increase the voltage generated by Mn17 so that Mn10/11 turn on and are in saturation.
You should also simulate in closed loop to find the proper DC operating point and not let the output rail. After you fix Mn10/11, then see what happens with Mp8/9
 
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