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question about PLL being in lock

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aka_rabbi

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I am designing a type-2 PLL on cadence. Check the attached picture please. The vco output freq. is divided by two before going into the PD. I have two questions-
1. the control voltage never stabilizes. why? the loop is not really achieving lock, is it?
2. can i put the sinusoidal output of the VCO to PFD directly?
pll.JPG
 

As I have seen, the Comparison Frequency OR Divided VCO Frequency is Swinging around so Phases are coincident but swinging to left and right.
I believe, you should decrease the min. Transient Analysis Time, I guess it's pretty coarse.

This can also be a Problem of Instability.Have you ever checked the Phase and Gain Margin ?? looks like it..
 
A PLO has a feedback loop, so it has to compensated to be stable, and not have the output oscillate in frequency.
Thus you must determine the phase and gain margin of the loop, as BB suggested.
 

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