fpga spartan 6 io ports are no longer working

HELLO there,

i have spartan 6 of the familyxlc9 but i am facing a severe problem with it . first i can burn successfully with jtag on it .its power is okay but the problem is whatever code i am burning to it

the io ports values doesn't change always all the pins are zeros except 4 pins that have values between 0.9 and 1.2 and another pin that have 3.3 .although the code is working on xillinx it is a simple code. trying to output ones on all the pins i changed the code to a code that does nothing like the fpga sends the same values on the output pins . i thought that those pins are no longer working

changed to another pins but all are zeros . it is like the output ports keeps a certain previous state and stand still.

i don't know does my fpga fails and has to be changed ? although jtag is burning code successfully

does spi flash memory is not working ? although i tried to upload the code on fpga directly and get the same output

thanks in advance

You can't just assign arbitrary values to all the user pins as outputs on any FPGA that is installed on a PCB. If the PCB has nothing on it but power you might be able to get away with doing that.

There is a chance you may have damaged the FPGA or the dev board by driving pins that should not have been driven.

ahmeddarwish252011 said:

HELLO there,

i have spartan 6 of the familyxlc9 but i am facing a severe problem with it . first i can burn successfully with jtag on it .its power is okay but the problem is whatever code i am burning to it

the io ports values doesn't change always all the pins are zeros except 4 pins that have values between 0.9 and 1.2 and another pin that have 3.3 .although the code is working on xillinx it is a simple code. trying to output ones on all the pins i changed the code to a code that does nothing like the fpga sends the same values on the output pins . i thought that those pins are no longer working

thanks in advance

Click to expand...

Hello,

in order to someone can help you you have to give more details:

1) Type and link to FPGA bord you are using for this code
2) JTAG programer: is it internal on-board or external (if yes give model)
3) What software are you using for synthesis and what version
4) Code of your project
5) Information if during synthesis/implementation phase are any errors or warnings?
6) What kind of output files are you generating (bit or bin file)
7) Are tehere any war4nings during loading programing file to FPGA (by JTAG)
8) Optionaly what OS are you using

These information should help to give you an answer.

Best Regards