mwb
Junior Member level 2
Hi, Im getting used to using "optimize_registers" in dc for retiming, everything that I'm doing seems to be working. However, I do get this output message during the optimization:
These messages show up for all the outputs and inputs.
I constrain the outputs with a set_load and the inputs with a set_drive. The input drive and output loads are realistic. Its a small circuit and I don't have a delay-spec for the outputs or inputs, just a loading and drive spec. Hows should I interpret these messages? I know that dc is pretty conservative with output warnings but I'd still like to get someone elses input before I go an ignore this. For the record, this is part of a mixed signal design; In virtuoso/spectre, the outputs look good.
Thanks
Code:
Warning: The output port 'CTL_SP[28]' has output rise and fall delay
that is smaller than the estimated average setup time used by the
retiming algorihm. For optimal results make sure to set an output
delay that is realistic. This can be done by using the
'set_output_delay' or 'characterize' commands. (RTDC-44)I constrain the outputs with a set_load and the inputs with a set_drive. The input drive and output loads are realistic. Its a small circuit and I don't have a delay-spec for the outputs or inputs, just a loading and drive spec. Hows should I interpret these messages? I know that dc is pretty conservative with output warnings but I'd still like to get someone elses input before I go an ignore this. For the record, this is part of a mixed signal design; In virtuoso/spectre, the outputs look good.
Thanks
