Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Mains setpoint monitoring basic circuit: best choice.

Status
Not open for further replies.
Akanimo said:
.....
So the divider is VRef= Vmains_rectfd*(R3+5k)/((R3+5k)+(R7+R2)) I believe.
Click to expand...
The divider voltage is the main's rectified average voltage, not the mains rectified voltage.
Akanimo said:
I think you meant that Vmains_rectfd = 0.5*((Vac*1.414) - 2*Vd)*2/pi.
Click to expand...
Yes.
Also, how does R_Hyst affect hysteresis? It affects it as a lonely component or with another component?
Click to expand...
It adds a small amount of positive feedback to the Ref node.
The amount of feedback is determined by the voltage divider between R_Hyst and the equivalent resistance at the Ref node.

I just noticed an error in the U3 pot connection.
Attached is the corrected schematic.

Capture.PNG
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top