Layout I/O modeling, LVS and density

Hi Team,
I am using TSMC 65nm CMOS technology to layout a mixed signal circuit. I am finishing up my layout with a few questions
1. I am planning to use the CUP(circuit under pad) pad with 60um pitch distance as my I/O pad. And I want to connect the pad to an ADC through wire-bonding and PCB. This is my first tape-out and I am worried my output stage's capability to drive the load. TSMC only offers a GDS file for pads without any schematic. Can anyone teach me how should I model the loading?

2. My circuit has 2 sets of supply. Ther are (0V GND ~ 1.2V VDD) and (-0.5V VSS ~ 2V VDD2.5). When I use calibre to run LVS, the calibre can only recognize one set of bias (0V GND ~ 1.2V VDD). Can anyone teach me how to run LVS with 2 power rails?

3. I am confused about metal density DRC. For now, I turned off the density check because I am under the impression that density can be fixed by the auto filler tool. And also some of the density rules are almost impossible to meet for higher metals, where I made the global connections. So Should I just leave the density apart and wait for the filler tool to fill in the circuit?

Thanks
Allen

1) You should be able to stream in the pad, extract the layout,
turn it into an analog_extracted view and make a corresponding
symbol, then set up a Spectre simulation and get whatever you
want from it. But there might be enough info in TSMC library
docs to skip all of that - don't they publish pad cell attributes
like min drive strength (perhaps as VOL@ILOAD) or maybe even
an IBIS model?

Ability to drive a (capacitive, as most are) load really depends
on frequency. I wouldn't go past 50MHz on a single ended CMOS
driver myself. But you don't say -what- circuit is under pad -
maybe it isn't even logic but some weak sauce analog signal
that will get its lunch money stolen by just the hum from
fluorescent lights. There's worse things than shunt C to Gnd,
and plenty of them. Maybe you should work backward from
the real world and what the ADC says its driver needs to
look like - some, especially high speed differential, seem to
have gotten pretty demanding about what you have to
feed them with, for part specs to apply.

2) This sounds wrong, or you've misused globals or some
other mis-design. You can route power as a signal or you
can use named! nets / global symbols (you should have
at least half a dozen not counting the gnd{}! ones). The
JI technology will need you to put the most negative
supply to the substrate and you may have the misfortune
to find that some library developer has made bad choices
for you, or required you to override things like the symbol
property for NMOS body connection. I have done many
multirail chips with no such problems.

3) Yes, density rules are stupidly demanding and all for the
fab rats' convenience. Anywhere you might care about the
local capacitance and couplings changing post-review, you
ought to place fills yourself. I liked to make my own fills as
plate capacitors, which at least are useful as decoupling.
In the end you will have to act humble and request waivers
once you have done your best.

Hi dick_freebird,
Thanks for your reply! Here are some follow-up comments and questions！
1) I could not find any information from the TSMC docs I have but I guess pex is my resort!
2) The major core part of my circuit is powered from 0V to 1.2V. However, my output amplifier alone is powered from -0.5V to 2V for enhanced output swing. When I LVS on the overall view, the Calibre LVS tool cannot recognize one of the power rails and report some power supply errors.
3) I also made my filler cell with substrate contact and bypass caps. I have 2 types: one is only M1(GND) and M2(VDD), the other is M1-M7 with M1357 as GND and M246 as VDD. I filled the whole circuit with filler cells. So my M1 and M2 density is fine but the density of the top metal is not as good since there are routings. Do you have any suggestions on how to fill the top metals? And have you used any auto-fill tools? I think that tool just generate dummy metal layers to meet with the density rule, am I right?

Allen