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Layout versus Schematic layout design issue

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Junus2012

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Dear friends,

in the next week I am going to start with my layout design. I have big fully differential amplifier circuit. I remember from my past work the problem when I finish with my layout and running the layout versus schematic then if I have an error it will be hard to identify and or more difficult to correct it. The difficulty will rise exponentially if the correction need to redesign some parts in the middle of the layout.

Is there an option in cadence where I can run the LVS at any level of my layout design by excluding the remaining of the circuit. Just as an example I would like to select to layout the differential pair transistors then I run the LVS, if LVS is ok then I continue to next transistors and so on. Such an option will be also useful to simulate the circuit at each added part of the layout.

I have tried similar kind of trick by dividing the circuit in many part and put every part in symbol and layout it individually, after then I connect the whole symbols to build back my circuit, but this method is mostly like designing digital system from different cells. However, in digital cells are mostly unique cells where one can connect them easily, not like the analog circuit cells.

Thank you very in advance
 

Of course it is and not only these features. The question is, whether you have an access to proper tools and/or licenses.

Using Virtuoso Layout XL/GXL there is a direct binding between nets and devices in schematic and layout, so tool showing in real time which connection are done properly, which are broken and where the shorts exists. Virtuoso Layout EAD/EXL allows real time extraction of current state of layout with EM/IR checks. Moreover, it allows to generates netlists for parasitic aware design flow to reduce number of desing steps/iterations.

I am pretty sure you have an access to Virtuoso Layout XL license, so the only thing you need to do is to read tool documentation (is in your cadence_IC_installation/doc/VXL/).
 
I like to build my layouts hierarchically, and DRC / LVS along
the way. So what if the cell is used only once and never
again?
 
Of course it is and not only these features. The question is, whether you have an access to proper tools and/or licenses.

Using Virtuoso Layout XL/GXL there is a direct binding between nets and devices in schematic and layout, so tool showing in real time which connection are done properly, which are broken and where the shorts exists. Virtuoso Layout EAD/EXL allows real time extraction of current state of layout with EM/IR checks. Moreover, it allows to generates netlists for parasitic aware design flow to reduce number of desing steps/iterations.

I am pretty sure you have an access to Virtuoso Layout XL license, so the only thing you need to do is to read tool documentation (is in your cadence_IC_installation/doc/VXL/).

Dear Dominik

Thank you for your suggestion,
Actually I have access to the Virtuoso Layout XL, I used before the property of monitoring the connection in real time, this procedure will work fine if I bring the transistor as it from the schematic, but as long as I divide it for matching it will become messy.
I never worked with EAD but I will try to search on it.

In short and as I understood from you, from the Layout XL I can check about the LVS without running the LVS, but by the option of real time monitoring the connections provided by XL environment.
To extract the parasitics at any partial level of the layout design.

- - - Updated - - -

I like to build my layouts hierarchically, and DRC / LVS along
the way. So what if the cell is used only once and never
again?

Dear freebird,

can you please tell me how to build the layouts hierarchically, I do it by splitting the circuit in to many symbols but as I said from my first post this procedure is also consuming time because then I have to connect these symbols. I was thinking to make the layouts hierarchically by layout some transistors in the same circuit but the LVS then start to complain about the non-layout transistors.

- - - Updated - - -

Let me please take this simple folded OTA as an example to make the answer more clear on how to build the circuit part by part hierarchically and checking the LVS continuously.

OtaN.png

- - - Updated - - -

in the image below I am showing you how I am dividing the circuit in to individual symbols, where every symbol is represented by the rectangular

OtaN.png
 

I would probably segment it similarly, but make the sink
current "repeaters" a single 3-sink cell (perhaps with
the bias master). But there's no wrong or right, just
what gets you down the road.
 
I would probably segment it similarly, but make the sink
current "repeaters" a single 3-sink cell (perhaps with
the bias master). But there's no wrong or right, just
what gets you down the road.

Dear Free_Bird,

Do you also put every segment in its own symbol or you have a different technique for that
 

Actually I have access to the Virtuoso Layout XL, I used before the property of monitoring the connection in real time, this procedure will work fine if I bring the transistor as it from the schematic, but as long as I divide it for matching it will become messy.
So, you doing it wrong. Proper usage of device parameters is your friend. As I remember correctly, you are using AMS C35 process, so NF and M are interchanging and there are no LDE (as far as I remember) parameters in device card. But, this is not a good practice to keep mess between schematic and layout. Especially, that in the advanced nodes you will not be allowed to not be VXL compliant and to has any mismatch between layout and schematic parameters.

Now think, if you facing the issue with proper connection of a very simple, few transistor circuit, how would you play with complicated IP?
The tools are not develop just for fun, they are driven by designer's needs.

In case to have nice CC matrix of, for example, diff-pair use proper M factor and keep device bindings between schematic and layout.
For bigger structures (like current steering DACs) use modgen tool (part of VXL). Even if such tools/flows seems to be less convenient than "classic" sculpturing, for more complicated designs or in advanced technologies becomes the only efficient way to work. And it is always a profit to learn a good practices.
 
Dear Dominik,

Thank you for your reply,

Yes I am using AMS 0.35 us technology,

I agree with what you have kindly explained to me. However, it is not possible to keep transistors in the layout as it exactly from the schematic. If your doupting that it is not good practice to use different number of gates in the layout than from the schematic (althaugh the W/L ratio is the same), then what about merging the common parts of the transistors ???

Just consider please this two simple common source differential pair transistors A and B. Suppose I would match it like (AB/BA) and I will merge the common source as shown in the image below.
Now the Layout drivin connectivity guidance from the Layout XL will not work, even after I do the LVS. for him to becoming like new circuit (althagh it doesnt complain in LVS), it needs every thing as it was in the schematic to guide me for the connection which is not possible for matching. I have worked with it today and I can confirm you this issue.

layout.jpg

Thhank you in advance
 

It's always a good idea to back-revise the schematic to
match the eventual reality of the layout. Don't make the
permute and parallel rules do any more thinking than they
must.
 
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