Hello,

I've designed a simple Ethernet stack that was working correctly on a Cyclone 10 FPGA (Evaluation board). During the migration to a Max 10 (Development board) I had a lot of problems implementing the same stack, my focus was always on the RGMII (MAC and PHY) as I thought the problem was located there.

At some point the design just started working (just testing the RGMII Tx for now). It just started sending UDP packets that I'm able to see using Wireshark. The problem is that the design only works in this exact code, if I change something non-related to the stack (for example removing the SignalTap instance) it just stops working. So I thought...this is probably a timing problem or a routing difference between both of the cases, but...I'm not able to find relevant differences. The RGMII Tx ports have the same slacks and timings, but maybe the problem is located in another place.

I'm very new to the "advanced" part of FPGAs and VHDL so I'm not still very good with TimeQuest. Any ideas?