+ Post New Thread
Results 1 to 8 of 8
  1. #1
    Member level 4
    Points: 1,100, Level: 7

    Join Date
    Jun 2015
    Posts
    75
    Helped
    0 / 0
    Points
    1,100
    Level
    7

    Convert from STD_LOGIC to integer in VHDL

    Is this code right?, I need to convert from STD_LOGIC to integer( to add those integers) and then back result to STD_LOGIC:
    a,h,f3,f0,k,w,f2,f1 are STD_Logic

    Code:
            a          <= std_logic_vector(to_unsigned((To_integer(unsigned(h)) +
                                                                                     To_integer(unsigned(f3)) + 
                                                                                     To_integer(unsigned(f0)) +
                                                                                     To_integer(unsigned(k)) + 
                                                                                     To_integer(unsigned(w))  + 
                                                                                     To_integer(unsigned(f2)) + 
                                                                                     To_integer(unsigned(f1))),a'length));

    •   AltAdvertisment

        
       

  2. #2
    Super Moderator
    Points: 255,118, Level: 100
    Awards:
    1st Helpful Member

    Join Date
    Jan 2008
    Location
    Bochum, Germany
    Posts
    44,452
    Helped
    13543 / 13543
    Points
    255,118
    Level
    100

    Re: Convert from STD_LOGIC to integer in VHDL

    Convert to integer makes no sense. Why not add unsigned?


    1 members found this post helpful.

    •   AltAdvertisment

        
       

  3. #3
    Full Member level 5
    Points: 2,171, Level: 10

    Join Date
    May 2014
    Posts
    253
    Helped
    27 / 27
    Points
    2,171
    Level
    10

    Re: Convert from STD_LOGIC to integer in VHDL

    std_logic but its nature is either 0 or 1.

    Do you mean std_logic_vector, furthermore when converting from interger back to std_logic_vector via unsigned you need to specify length


    1 members found this post helpful.

    •   AltAdvertisment

        
       

  4. #4
    Newbie level 3
    Points: 53, Level: 1

    Join Date
    Mar 2019
    Posts
    4
    Helped
    1 / 1
    Points
    53
    Level
    1

    Re: Convert from STD_LOGIC to integer in VHDL

    Here you can find examples with all the important VHDL conversions:
    https://www.nandland.com/vhdl/tips/t...o-integer.html
    I don't think that you can convert an std_logic to integer, you will probably need to use std_logic_vector signals of a single bit, like: signal names : std_logic_vector(0 downto 0);


    1 members found this post helpful.

  5. #5
    Member level 4
    Points: 1,100, Level: 7

    Join Date
    Jun 2015
    Posts
    75
    Helped
    0 / 0
    Points
    1,100
    Level
    7

    Re: Convert from STD_LOGIC to integer in VHDL

    Quote Originally Posted by FvM View Post
    Convert to integer makes no sense. Why not add unsigned?
    I tried this:
    a <= std_logic_vector(unsigned(h) +unsigned(f3) + unsigned(f0) +unsigned(k) + unsigned(w) + unsigned(f2) + unsigned(f1));

    and i still have these errors "Bad expression in left operand of infix expression "+".
    (vcom-1078) Identifier "unsigned" is not directly visible.
    Illegal type conversion to ieee.std_logic_1164.STD_LOGIC_VECTOR (operand type is not known).



    •   AltAdvertisment

        
       

  6. #6
    Advanced Member level 5
    Points: 37,449, Level: 47
    Achievements:
    7 years registered

    Join Date
    Jun 2010
    Posts
    6,805
    Helped
    1997 / 1997
    Points
    37,449
    Level
    47

    Re: Convert from STD_LOGIC to integer in VHDL

    "Bad expression in left operand of infix expression "+".
    (vcom-1078) Identifier "unsigned" is not directly visible.
    This error is because you have more than one package that declares an unsigned type. You didnt post the code, but I assume you have included std_logic_arith and numeric_std. You should delete std_logic_arith as it is a non-standard VHDL library.

    You have another problem: you're trying to convert std_logic to unsigned. Thats impossible, because std_logic is an enumerated type, and unsigned is an array of std_logic. They are not related types.
    You will need to make an array out of your single std_logic bits to make them unsigned. There is a nice little hack for this - simply append the bit to a null array. You will also need to qualify the resulting array as unsigned so it doesnt get confused between unsigned and signed:

    Code VHDL - [expand]
    1
    
    a <= std_logic_vector( unsigned'(""&h) + unsigned(""&f3) ....... etc

    Of course, it would have been much easier if a and the other signals were all unsigned in the first place.


    1 members found this post helpful.

  7. #7
    Super Moderator
    Points: 30,484, Level: 42
    ads-ee's Avatar
    Join Date
    Sep 2013
    Location
    USA
    Posts
    7,013
    Helped
    1677 / 1677
    Points
    30,484
    Level
    42

    Re: Convert from STD_LOGIC to integer in VHDL

    what libraries are you using?

    ...you are probably using the ieee.numeric_std along with the conflicting synopsys libraries ieee.std_logic_arith and ieee.std_logic_unsigned.

    I've been having a similar problem due to a very old testbench and the need to use some code that requires numeric_std, so I've had to resort to explicitly calling out what functions are used instead of using .all, very annoying.


    1 members found this post helpful.

  8. #8
    Member level 4
    Points: 1,100, Level: 7

    Join Date
    Jun 2015
    Posts
    75
    Helped
    0 / 0
    Points
    1,100
    Level
    7

    Re: Convert from STD_LOGIC to integer in VHDL

    Quote Originally Posted by TrickyDicky View Post
    This error is because you have more than one package that declares an unsigned type. You didnt post the code, but I assume you have included std_logic_arith and numeric_std. You should delete std_logic_arith as it is a non-standard VHDL library.

    You have another problem: you're trying to convert std_logic to unsigned. Thats impossible, because std_logic is an enumerated type, and unsigned is an array of std_logic. They are not related types.
    You will need to make an array out of your single std_logic bits to make them unsigned. There is a nice little hack for this - simply append the bit to a null array. You will also need to qualify the resulting array as unsigned so it doesnt get confused between unsigned and signed:

    Code VHDL - [expand]
    1
    
    a <= std_logic_vector( unsigned'(""&h) + unsigned(""&f3) ....... etc

    Of course, it would have been much easier if a and the other signals were all unsigned in the first place.
    Thank you so much
    It is solved

    - - - Updated - - -

    Quote Originally Posted by ads-ee View Post
    what libraries are you using?

    ...you are probably using the ieee.numeric_std along with the conflicting synopsys libraries ieee.std_logic_arith and ieee.std_logic_unsigned.

    I've been having a similar problem due to a very old testbench and the need to use some code that requires numeric_std, so I've had to resort to explicitly calling out what functions are used instead of using .all, very annoying.
    Thank you so much
    It is solved



--[[ ]]--