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Verilog beginner: is synthetized rtl optimal?

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Joel_Damato

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Hi,

For that source code:
Code:
module top(input clk, input led, output to_port1,output [24:0] to_port2);
   
    reg ctr = 0;
	reg[24:0] counter = 2;
    always@(posedge clk) begin
		if (ctr == 1) begin
			ctr <= 0;
			counter <= counter + 1;
		end
		else
			ctr <= 1;
    end

    assign led = ctr;
	assign to_port1 = led;
	assign to_port2 = counter;
endmodule

I used Yosys to generate rtl. It gave me this:
Code:
/* Generated by Yosys 0.8 (git sha1 UNKNOWN, clang 7.0.2 -fPIC -Os) */

(* src = "x.v:1" *)
module top(clk, led, to_port1, to_port2);
  (* src = "x.v:5" *)
  reg [24:0] _0_;
  (* src = "x.v:5" *)
  reg _1_;
  (* src = "x.v:4" *)
  reg [24:0] _2_;
  (* src = "x.v:3" *)
  reg _3_;
  (* src = "x.v:8" *)
  wire [31:0] _4_;
  (* src = "x.v:6" *)
  wire _5_;
  (* src = "x.v:1" *)
  input clk;
  (* src = "x.v:4" *)
  reg [24:0] counter;
  (* src = "x.v:3" *)
  reg ctr;
  (* src = "x.v:1" *)
  input led;
  (* src = "x.v:1" *)
  output to_port1;
  (* src = "x.v:1" *)
  output [24:0] to_port2;
  assign _4_ = counter + (* src = "x.v:8" *) 32'd1;
  assign _5_ = ctr == (* src = "x.v:6" *) 32'd1;
  always @* begin
    _3_ = 1'h0;
  end
  always @* begin /*useless?*/
  end
  always @({  }) begin
      ctr <= _3_;
  end
  always @* begin
    _2_ = 25'h0000002; /* proper way to initialize a value?
  end
  always @* begin /*useless?*/
  end
  always @({  }) begin
      counter <= _2_; /* _2_ is always equal to 2, no?*/ 
  end
  always @* begin
    _1_ = ctr;
    _0_ = counter;
    casez (_5_) /* counter overflow management */
      1'h1:
        begin
          _1_ = 1'h0;
          _0_ = _4_[24:0];
        end
      default:
          _1_ = 1'h1;
    endcase
  end
  always @(posedge clk) begin
      ctr <= _1_;
      counter <= _0_;
  end
  assign led = ctr;
  assign to_port1 = led;
  assign to_port2 = counter;
endmodule

I annotated the code so that you can see where my interrogations lie.
Would you consider it is a reasonable rtl code?

Thanks
 

I think you should spend some more time with your Verilog.

You are assigning the value of a register to an input port?
assign led = ctr;

Did you try to compile your code before this Yosis stuff?
It would be meaningless to do synthesis with error RTL.
 

You are right. Overlooked that.
Here is the corrected code and the new synthesis:
Code:
module top(input clk, input led, output led2, output to_port1,output [24:0] to_port2);
   
    reg ctr = 0;
	reg[24:0] counter = 2;
    always@(posedge clk) begin
		if (ctr == 1) begin
			ctr <= 0;
			counter <= counter + 1;
		end
		else
			ctr <= 1;
    end

    assign led2 = ctr;
	assign to_port1 = led;
	assign to_port2 = counter;
endmodule

Code:
module top(clk, led, led2, to_port1, to_port2);

  reg [24:0] _0_;

  reg _1_;

  reg [24:0] _2_;

  reg _3_;

  wire [31:0] _4_;

  wire _5_;

  input clk;

  reg [24:0] counter;

  reg ctr;

  input led;

  output led2;

  output to_port1;

  output [24:0] to_port2;
  assign _4_ = counter + 32'd1;
  assign _5_ = ctr == 32'd1;
  always @* begin
    _3_ = 1'h0;
  end
  always @* begin
  end
  always @({  }) begin
      ctr <= _3_;
  end
  always @* begin
    _2_ = 25'h0000002;
  end
  always @* begin
  end
  always @({  }) begin
      counter <= _2_;
  end
  always @* begin
    _1_ = ctr;
    _0_ = counter;
    casez (_5_)
      1'h1:
        begin
          _1_ = 1'h0;
          _0_ = _4_[24:0];
        end
      default:
          _1_ = 1'h1;
    endcase
  end
  always @(posedge clk) begin
      ctr <= _1_;
      counter <= _0_;
  end
  assign led2 = ctr;
  assign to_port1 = led;
  assign to_port2 = counter;
endmodule

So, the problem is that it generates empty lists
Code:
This @* expands to empty list, will never wake up.

So basically, the rtl is not good when the original code simulates just fine. Where did I messed up?
 

First please tell me what is your need, your target.
Are you trying to <1> write a good RTL or <2> are you trying to test the Yosys tool for a good netlist generation?

If <1>, you should be writing a test-bench and performing functional verification of your design through simulation.
If <2>, You can easily get a correct and properly coded simple 'counter' code from the internet and use it with Yosys.

FYI - I rarely take a look into synthesized netlist files and this is the first time I am hearing about this Yosys.
 

Thanks Dpaul, I am just tinkering with the tool, throwing random code at it..
 

Writing better RTL that is easy to understand is more important than what it ends up looking like.
Hard to understand but "clever" RTL is more likely to get thrown away by others.
Learn to write RTL, and the circuit improvement should come with it.
 

...throwing random code at it.
I think you should be first putting in good quality and verified RTL (there are many trusted sources, Google) and use them.
Then for playing around and see how the tool is behaving, you can try throwing in bad RTL.

Remember one thing, if you are posting here netlists and its corresponding RTL, and asking us to evaluate the netlist quality, that is not feasible. As I have mentioned before, design engineers rarely look inside a netlist.
 
Last edited:

Why is the output of synthesis not a netlist? What am I missing here?
 

Why is the output of synthesis not a netlist? What am I missing here?

I know it looks more like obfuscated RTL with all the "_1_" translated names.

Netlists never have always, case, or other behavioral code keywords.
 

It looks like the first synthesis stage, independent of hardware/architecture.
 

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