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    Synth. area reduced when adding a pipeline register

    I'm synthesizing a Verilog design in Design Compiler. I'm adding a relatively tight timing constraint. The reported area is quite big. When I try to break the critical path by manually adding an additional register, the area is reduced by a large factor. Any explanation?

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    Re: Synth. area reduced when adding a pipeline register

    Misnaming a connection (wrong case) and DC finds a unconnected signal and boom it deletes a bunch of logic as "unused".



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    Re: Synth. area reduced when adding a pipeline register

    Quote Originally Posted by ads-ee View Post
    Misnaming a connection (wrong case) and DC finds a unconnected signal and boom it deletes a bunch of logic as "unused".
    I don't think this is the case (I checked for unconnected nets). It looks like DC is trying so hard to reach the timing constraint in the first case, but results in getting an unoptimized area. When I cut the design with one level of registers, this seems to help DC find a better area. I'm not sure though, so feel free to correct me if I'm wrong.



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    Re: Synth. area reduced when adding a pipeline register

    DC will generate a synth report.
    Have you investigated the DC generated reports in both cases?
    Your answer is likely to be there in the reports.....
    FPGA enthusiast!



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    Re: Synth. area reduced when adding a pipeline register

    Quote Originally Posted by oAwad View Post
    I'm synthesizing a Verilog design in Design Compiler. I'm adding a relatively tight timing constraint. The reported area is quite big. When I try to break the critical path by manually adding an additional register, the area is reduced by a large factor. Any explanation?
    if the constraint is super tight, close to the maximum, several paths can be overly buffered to achieve the target. if you relax the constraint by splitting the path, you are inserting one flop, but maybe removing several buffers and oversized cells. this type of trade-off is very common, there is nothing wrong about it.
    Really, I am not Sam.



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