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    Spartan6 (ISE 14.7) how to generate differential clock?

    Hello,

    I would like to ask: How to generate differential (two lines) clock from "normal" clock (one line). The clock frequency is 100 MHz. Project is written in Verilog and I am using
    "ISE Webpack 14.7" (Windows10 Pro) for synthessis. My FPGA is Spartan6 (XC6SLX9 in CSG324 package) on Mimas V.2 board (Numato).

    Thanks in advance and Regards

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    Re: Spartan6 (ISE 14.7) how to generate differential clock?

    By choosing a suitable differential output pin pair and the respective differential IO standard in constraint editor.



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    Re: Spartan6 (ISE 14.7) how to generate differential clock?

    Quote Originally Posted by FvM View Post
    By choosing a suitable differential output pin pair and the respective differential IO standard in constraint editor.
    Hello,

    I thought that differential clok is consisted from two signal lines. Signal on second line is square wave shifted in phase for 180 degrees in relation to signal on first line.
    I know that in user constraint files are appropriate standards for this (for example DIFF_MOBILE_DDR).

    If i have one line clock from PLL, I don't need to generate second signal? I am a bit confusing now, could you clarify this question?

    Thanks nad Regards



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    Re: Spartan6 (ISE 14.7) how to generate differential clock?

    The inverted signal is generated in IO cell, the usual way is to have one output signal (e.g. a top level port of your design) and assign a differential IO standard to it. I have only cursory knowledge of Xilinx tools, but I have seen this method used with it.

    Alternatively, there may be an option to instantiate a differential driver low level primitive explicitly, but it doesn't bring any advantage in usual cases.


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    Re: Spartan6 (ISE 14.7) how to generate differential clock?

    An OBUFDS Xilinx primitive might suite your purpose.
    I would suggest you to read the realted "SelectIO Resources" docu for Series6 Xilinx FPGA for details.

    This thread might help : https://forums.xilinx.com/t5/Spartan...ck/td-p/100268
    FPGA enthusiast!


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    Re: Spartan6 (ISE 14.7) how to generate differential clock?

    Quote Originally Posted by dpaul View Post
    An OBUFDS Xilinx primitive might suite your purpose.
    I would suggest you to read the realted "SelectIO Resources" docu for Series6 Xilinx FPGA for details.

    This thread might help : https://forums.xilinx.com/t5/Spartan...ck/td-p/100268
    Hello,

    I placed in my Verilog code OBUFDS instance like that:


    Code:
    wire CLOCK_OUT_P,CLOCK_OUT_N;
    
    
      CLKWizard CLKGEN
       (// Clock in ports
        .CLK_IN1(Clk100Mhz),     
        // Clock out ports
        .CLK_OUT1(clkAXIOut),    //50 MHz AXI clock
        .CLK_OUT2(clkVGAOut),    //25.175 MHz VGA clock
        .CLK_OUT3(clkBuf100MHz), //100 MHz DDR memory clock 
        // Status and control signals
        .RESET(io_asyncReset),
        .LOCKED(clkLOCKED));  
    	 
    	 //buf clkBuffer(clkBuf100MHz,clkDDR100MHz);
    	 
      OBUFDS #(
      .IOSTANDARD("DIFF_MOBILE_DDR")
      ) OBUFDS_01 (
       .O(CLOCK_OUT_P),
       .OB(CLOCK_OUT_N),
       .I(clkBuf100MHz)
      );
    and project (ISE 14.7) implements without errors, so I assume that it is all right.

    Thanks for help and Regards



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    Re: Spartan6 (ISE 14.7) how to generate differential clock?

    and project (ISE 14.7) implements without errors, so I assume that it is all right.
    If there are no more problems then it is time to close the thread!
    FPGA enthusiast!



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