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what $finish will be sythesis to in verilog?

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liletian

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Hi All

For the digital computer, there always has a halt mode which basically mean to turn off the system.

In the verilog, a $finish is used in verilog code.

I am just wondering how the synthesizer will synthesize this to?

Thanks

Brian
 

Hi All

For the digital computer, there always has a halt mode which basically mean to turn off the system.

In the verilog, a $finish is used in verilog code.

I am just wondering how the synthesizer will synthesize this to?

Thanks

Brian

$finish is not synthesizable. nothing will be generated.
 

The $finish is a system task, which is used to stop the simulation. It shouldn't be used in the RTL, but in test bench (so in a code that will not be synthetized).

Depending on your design, you can control some exernal switches, power-downs or another circuits to enter the low power mode (or to cut the power supply as ThisIsNotSam wrote).
 

The circuitry to do this goes beyond what you could describe in plain digital Verilog. Power is analog,
 

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