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    what $finish will be sythesis to in verilog?

    Hi All

    For the digital computer, there always has a halt mode which basically mean to turn off the system.

    In the verilog, a $finish is used in verilog code.

    I am just wondering how the synthesizer will synthesize this to?

    Thanks

    Brian

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    Re: what $finish will be sythesis to in verilog?

    Quote Originally Posted by liletian View Post
    Hi All

    For the digital computer, there always has a halt mode which basically mean to turn off the system.

    In the verilog, a $finish is used in verilog code.

    I am just wondering how the synthesizer will synthesize this to?

    Thanks

    Brian
    $finish is not synthesizable. nothing will be generated.
    Really, I am not Sam.



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  3. #3
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    Re: what $finish will be sythesis to in verilog?

    Quote Originally Posted by ThisIsNotSam View Post
    $finish is not synthesizable. nothing will be generated.
    so in the real processor, how do they handle this the shutdown?

    Thanks,

    Brian



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    Re: what $finish will be sythesis to in verilog?

    Quote Originally Posted by liletian View Post
    so in the real processor, how do they handle this the shutdown?

    Thanks,

    Brian
    Just cut the power supply and you are done.
    Really, I am not Sam.



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    Re: what $finish will be sythesis to in verilog?

    The $finish is a system task, which is used to stop the simulation. It shouldn't be used in the RTL, but in test bench (so in a code that will not be synthetized).

    Depending on your design, you can control some exernal switches, power-downs or another circuits to enter the low power mode (or to cut the power supply as ThisIsNotSam wrote).



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  6. #6
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    Re: what $finish will be sythesis to in verilog?

    The circuitry to do this goes beyond what you could describe in plain digital Verilog. Power is analog,
    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation



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