I have two clocks in my design where I am not sure how to define them properly:

A)

I have created generated clock CLK_A and CLK_C, but I am not sure how to define CLK_B.

CLK_A and CLK_C are asynchronous clock domains
CLK_A is gated generated clock from primary clock 1
CLK_C is gated generated clock from primary clock 2
CLK_B is used only to latch the event until it is detected by the FF in CLK_C clock domain.


B)
CLK is generated by combination of two inputs (used as data in all other clock domains) and gated to one by the output of shift register.

I have defined PORT A and PORT B as primaray clocks, but I am not sure how to define CLK

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