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    DAC Jitter Modeling for CTSD Modulator

    Hello,

    I was implementing a 5 bit DAC to be used in a CT sigma delta modulator. I would like to model the error due to clk Jitter at the output of the DAC in VerilogA. Any Ideas?

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    Re: DAC Jitter Modeling for CTSD Modulator

    Use ideal DAC and clock with jitter.


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    Re: DAC Jitter Modeling for CTSD Modulator

    Quote Originally Posted by pancho_hideboo View Post
    Use ideal DAC and clock with jitter.
    Since, I am new to verilogA, could you tell me How to model Clock with jitter?



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    Re: DAC Jitter Modeling for CTSD Modulator



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    Re: DAC Jitter Modeling for CTSD Modulator

    Hi,

    Do you know How to add mismatch to the DAC Model that calculates the value each clock?

    Thanks



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    Re: DAC Jitter Modeling for CTSD Modulator

    Quote Originally Posted by RamyRady_RF View Post
    Do you know How to add mismatch to the DAC Model that calculates the value each clock?
    Generate random number.



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