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    [moved] Inferring latches issue

    Hello,
    I'm kind of new to electronics. I'm working on a project for school. I created some VHDL code, simulated it on a Modelsim Altera waveform, and everything worked correctly. I am now trying to use Quartus II to simulate it on an Altera DE2-115 board. I connect the amount std_logic_vector to 10 LEDs on the board (so as to read it in binary), and the LEDs don't light up at all how I expect. I have no clue why, since it works fine on the Modelsim Altera simulation. I am using this Entity as a component in another VHDL file, but I'm positive the problem is not there. I don't get why it says "Pin ___ is stuck at (VCC or GND)." Also, ignore the fact that some connections aren't connected. Here is the code for the VHDL file in question and what is output form Quartus II when I compile the project:

    Code:

    Code VHDL - [expand]
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    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
     
    Entity BetController is
      port(CLK, addToBet, confirmBet : in std_logic;
           amount,total: out std_logic_vector(9 downto 0));
    End Entity BetController;
     
    Architecture Behavioral of BetController is
      type state is (s0,s1);
        
      signal x: integer range 0 to 1000 := 0;
      signal y: integer range 0 to 1000 := 100;
      signal FS: state := s0;
      signal PS: state := s0;
      signal iamount, itotal : unsigned(9 downto 0) := "0000000000";
      begin
        process (CLK)
          begin
          if rising_edge (CLK) then
                PS <= FS;
            end if;
      end process;
      process (PS, addToBet, confirmBet)
        begin
            case PS is
            when s0 =>
              if((addToBet = '0' and confirmBet = '0') or (addToBet = '0' and confirmBet = '1')) then
                FS <= s1;
              else
                FS <= s0;
              end if;
            when s1 =>
              if((addToBet = '1' and confirmBet = '1') or (addToBet = '1' and confirmBet = '0')) then
                x <= x + 10;
                y <= y - 10;
                FS <= s0;
              else
                FS <= s1;
                end if;
            end case;
        end process;
           
      iamount <= to_unsigned(x, 10);
      itotal <= to_unsigned(y, 10);
      amount <= std_logic_vector(iamount);
      total <= std_logic_vector(itotal);
      end Architecture Behavioral;

    Compile

    Code:
    Warning (335093): TimeQuest Timing Analyzer is analyzing 8 combinational loops as latches.
    Warning (335093): TimeQuest Timing Analyzer is analyzing 8 combinational loops as latches.
    Warning (332125): Found combinational loop of 2 nodes
    	Warning (332126): Node "bet_control|intAmount[1]~0|combout"
    	Warning (332126): Node "bet_control|intAmount[1]~0|dataa"
    	Warning (332126): Node "bet_control|intAmount[1]~0|combout"
    	Warning (332126): Node "bet_control|intAmount[1]~0|dataa"
    Warning (332125): Found combinational loop of 2 nodes
    	Warning (332126): Node "bet_control|intAmount[1]~0|combout"
    	Warning (332126): Node "bet_control|intAmount[1]~0|datab"
    	Warning (332126): Node "bet_control|intAmount[1]~0|combout"
    	Warning (332126): Node "bet_control|intAmount[1]~0|datab"
    Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
    Warning (21074): Design contains 11 input pin(s) that do not drive logic
    	Warning (15610): No output dependent on input pin "CLR"
    	Warning (15610): No output dependent on input pin "button1"
    	Warning (15610): No output dependent on input pin "gameSelect[0]"
    	Warning (15610): No output dependent on input pin "gameSelect[1]"
    	Warning (15610): No output dependent on input pin "guessSwitches[0]"
    	Warning (15610): No output dependent on input pin "guessSwitches[1]"
    	Warning (15610): No output dependent on input pin "guessSwitches[2]"
    	Warning (15610): No output dependent on input pin "guessSwitches[3]"
    	Warning (15610): No output dependent on input pin "guessSwitches[4]"
    	Warning (15610): No output dependent on input pin "guessSwitches[5]"
    	Warning (15610): No output dependent on input pin "guessSwitches[6]"
    	Warning (15610): No output dependent on input pin "CLR"
    	Warning (15610): No output dependent on input pin "button1"
    	Warning (15610): No output dependent on input pin "gameSelect[0]"
    	Warning (15610): No output dependent on input pin "gameSelect[1]"
    	Warning (15610): No output dependent on input pin "guessSwitches[0]"
    	Warning (15610): No output dependent on input pin "guessSwitches[1]"
    	Warning (15610): No output dependent on input pin "guessSwitches[2]"
    	Warning (15610): No output dependent on input pin "guessSwitches[3]"
    	Warning (15610): No output dependent on input pin "guessSwitches[4]"
    	Warning (15610): No output dependent on input pin "guessSwitches[5]"
    	Warning (15610): No output dependent on input pin "guessSwitches[6]"
    Warning (20028): Parallel compilation is not licensed and has been disabled
    Warning (20028): Parallel compilation is not licensed and has been disabled
    Warning (20028): Parallel compilation is not licensed and has been disabled
    Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
    Warning (13024): Output pins are stuck at VCC or GND
    	Warning (13410): Pin "LEDbet1[0]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[0]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[1]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[2]" is stuck at VCC
    	Warning (13410): Pin "LEDbet2[3]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[4]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[5]" is stuck at VCC
    	Warning (13410): Pin "LEDbet2[6]" is stuck at VCC
    	Warning (13410): Pin "LEDbet2[7]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[8]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[9]" is stuck at GND
    	Warning (13410): Pin "LEDbet1[0]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[0]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[1]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[2]" is stuck at VCC
    	Warning (13410): Pin "LEDbet2[3]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[4]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[5]" is stuck at VCC
    	Warning (13410): Pin "LEDbet2[6]" is stuck at VCC
    	Warning (13410): Pin "LEDbet2[7]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[8]" is stuck at GND
    	Warning (13410): Pin "LEDbet2[9]" is stuck at GND
    Warning (10631): VHDL Process Statement warning at BetController.vhd(28): inferring latch(es) for signal or variable "intAmount", which holds its previous value in one or more paths through the process
    Warning (10540): VHDL Signal Declaration warning at BetController.vhd(17): used explicit default value for signal "intTotal" because signal was never assigned a value
    Warning (10492): VHDL Process Statement warning at BetController.vhd(39): signal "intAmount" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
    Critical Warning (332148): Timing requirements not met
    	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
    	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
    Critical Warning (332148): Timing requirements not met
    	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
    	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
    Critical Warning (332148): Timing requirements not met
    	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
    	Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
    Critical Warning (332012): Synopsys Design Constraints File file not found: 'Interface.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
    Critical Warning (332012): Synopsys Design Constraints File file not found: 'Interface.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
    Critical Warning (169085): No exact pin location assignment(s) for 36 pins of 51 total pins
    	Info (169086): Pin CLR not assigned to an exact location on the device
    	Info (169086): Pin gameSelect[0] not assigned to an exact location on the device
    	Info (169086): Pin gameSelect[1] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[0] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[1] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[2] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[3] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[4] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[5] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[6] not assigned to an exact location on the device
    	Info (169086): Pin winLED not assigned to an exact location on the device
    	Info (169086): Pin loseLED not assigned to an exact location on the device
    	Info (169086): Pin ssd1[0] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[1] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[2] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[3] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[4] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[5] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[6] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[0] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[1] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[2] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[3] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[4] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[5] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[6] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[0] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[1] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[2] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[3] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[4] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[5] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[6] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[7] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[8] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[9] not assigned to an exact location on the device
    	Info (169086): Pin CLR not assigned to an exact location on the device
    	Info (169086): Pin gameSelect[0] not assigned to an exact location on the device
    	Info (169086): Pin gameSelect[1] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[0] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[1] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[2] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[3] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[4] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[5] not assigned to an exact location on the device
    	Info (169086): Pin guessSwitches[6] not assigned to an exact location on the device
    	Info (169086): Pin winLED not assigned to an exact location on the device
    	Info (169086): Pin loseLED not assigned to an exact location on the device
    	Info (169086): Pin ssd1[0] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[1] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[2] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[3] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[4] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[5] not assigned to an exact location on the device
    	Info (169086): Pin ssd1[6] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[0] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[1] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[2] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[3] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[4] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[5] not assigned to an exact location on the device
    	Info (169086): Pin ssd2[6] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[0] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[1] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[2] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[3] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[4] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[5] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[6] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[7] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[8] not assigned to an exact location on the device
    	Info (169086): Pin LEDbet2[9] not assigned to an exact location on the device
    Last edited by ads-ee; 20th April 2019 at 01:04. Reason: changed to syntax tags so it's easier to read the code

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  2. #2
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    Re: [moved] Inferring latches issue

    Your compile log does not match the code you've posted.

    - - - Updated - - -

    The x <= x + 10 and the y <= y - 10 will require latches as the outputs are feed back to the input but there isn't a FF being used to store the x and y values.

    This is why using the two process FSM style can backfire if you don't know what you are doing or are learning. If you use a one process FSM then you'll end up with FFs on all the FSM outputs and you won't have latches.



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  3. #3
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    Re: [moved] Inferring latches issue

    x, y are also combinatorial loops because they are in the combinatorial process.

    Code:
    process (CLK)
    begin
      if rising_edge (CLK) then
        PS <= FS; -- good, but there should be a reset
        -- x <= next_x;
        -- y <= next_y;
      end if;
    end process;
    process (PS, addToBet, confirmBet) -- if VHDL2008 is supported, there is process (all)
                                       -- Simulation mismatches can occur if a value is read in
                                       -- the process without being in this list.
    begin
      -- At this point in the process, you should have "FS <= PS".  This is very convenient.
      -- also, next_x <= x; next_y <= y;
      case PS is
      when s0 =>
        if((addToBet = '0' and confirmBet = '0') or (addToBet = '0' and confirmBet = '1')) then
          FS <= s1;
        else
          FS <= s0; -- no longer needed -- the assignment happened above
        end if;
      when s1 =>
        if((addToBet = '1' and confirmBet = '1') or (addToBet = '1' and confirmBet = '0')) then
          x <= x + 10; -- should be next_x <= x + 10;
          y <= y - 10; -- should be next_y <= y - 10;
          FS <= s0;
        else
          FS <= s1; -- no longer needed -- done at the start of the process.
        end if;
      end case;
    end process;
    This is one example of how this could be written.

    IMO, this sub-topic of FSM design can also be described with two questions -- "how much next state/logic is described in a combinatorial process?" and "how many signals are driven in the fsm case statement?" All four corners have pros/cons making them tools that an engineer can use vs one being strictly superior.

    The one-process fsm where all signals are in the fsm case statement is the most catastrophe prone, but it is very fashionable. For students it is probably the worst choice -- it is easy to write logic in the case statement with the intent of writing logic for that case vs the transition to the next state. The one-process fsm with only the state logic in the case statement is better in this regard, but now the other logic is hard to write and prone to a lot of copy-paste by students. With verilog-2001 or vhdl-2008 having just the fsm logic be two-process generally makes other clocked logic easier to write and adds only a few lines of code. The full two-process style is very boilerplate and common error prone. There are some things that experienced users can do to make this less of an issue, but students are normally not experienced users.



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  4. #4
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    Re: [moved] Inferring latches issue

    The one-process fsm where all signals are in the fsm case statement is the most catastrophe prone, but it is very fashionable.
    I think, the potential catastrophes are foreseeable and can be avoided if you clearly plan ahead the intended function. It's straightforward to have one case structure that enumerates all states, containing both the state transitions and state specific actions. That particularly eases later modifications of the state logic. e.g. inserting new states.

    Needless to say that the present exercise problem can be perfectly coded in a single process FSM. But may be two-process is required.



  5. #5
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    Re: [moved] Inferring latches issue

    I think, the potential catastrophes are foreseeable and can be avoided if you clearly plan ahead the intended function.
    Does this really sound like students?

    But may be two-process is required.
    it does look like the design has unregistered outputs. Although it isn't clear if that was part of the spec. If so, two-process gets a little more attractive.



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