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  1. #1
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    6T SRAM read/write current

    Hi,

    I'm having trouble finding data regarding SRAM read/write currents for 7nm nodes.
    Most of the results/data I've seen seem to be done on larger technology nodes, or on the noise margins.

    Currently, at most I've found that read/write currents are around 40~60 uA for Vdd=1V, but I think they might be too large?

    Does anyone have data off the top of their heads, or could point me to some conference/journal/roadmap where I can find the data?

    Thanks!

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  2. #2
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    Re: 6T SRAM read/write current

    Quote Originally Posted by Windywast View Post
    Hi,

    I'm having trouble finding data regarding SRAM read/write currents for 7nm nodes.
    Most of the results/data I've seen seem to be done on larger technology nodes, or on the noise margins.

    Currently, at most I've found that read/write currents are around 40~60 uA for Vdd=1V, but I think they might be too large?

    Does anyone have data off the top of their heads, or could point me to some conference/journal/roadmap where I can find the data?

    Thanks!
    very few people have access to 7nm, and even fewer would be in a position where they can share these values. I can tell it certainly doesn't operate at 1V, nominal voltage is <0.8V.
    Really, I am not Sam.



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  3. #3
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    Re: 6T SRAM read/write current

    Peak write current will be found at the "tipping point"
    of the core cross-coupled inverters. You could mock
    this up with min W, min L devices (although SRAM
    leaf cells are often allowed to "cheat" specific rules
    in the name of density, and you might not get to know
    (say) that the min W is less than LGRP min W unless
    you have gotten the PDK and library info from the real
    foundry).

    You might find "write charge" more useful than a write
    current, peak or averaged. Flipping over a bit (write) or
    reading a bit both act like a charge-slug per event,
    gross supply current is leakage plus these "events"
    and largely frequency dependent (as most CMOS).

    Of course in SRAM detailed design the worst case write
    current (peak) is what the write network has to source
    or sink, through the access switches, and read current
    obtainable without read turning into false write, drives
    the sense line loading, precharge and sense amp design.

    Whether this is about specification / characterization,
    or about design, is not told.



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