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8 Bit Matrix Multiplication in Verilog

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Shanks100

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Hey Guys, I'm trying to Implement a program to multiply two matrices(8 bit)( 5x5 ) and I'm stuck trying to complete this code. It would be awesome if you guys could help me on this. The code is Posted Below:

Code Verilog - [expand]
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module matrixmult(A,B,C);
input[7:0]A;
input[7:0]B;
output[15:0]C;
integer i;
integer j;
integer k;
reg [7:0] A01 [0:4][0:4];
reg [7:0] B01 [0:4][0:4];
reg [7:0] C01 [0:4][0:4]; 
initial begin
reg [7:0] A11; //INPUT A
reg [7:0] A12;
reg [7:0] A13;
reg [7:0] A14;
reg [7:0] A15;
reg [7:0] A21;
reg [7:0] A22;
reg [7:0] A23;
reg [7:0] A24;
reg [7:0] A25;
reg [7:0] A31;
reg [7:0] A32;
reg [7:0] A33;
reg [7:0] A34;
reg [7:0] A35;
reg [7:0] A41;
reg [7:0] A42;
reg [7:0] A43;
reg [7:0] A44;
reg [7:0] A45;
reg [7:0] A51;
reg [7:0] A52;
reg [7:0] A53;
reg [7:0] A54;
reg [7:0] A55;
reg [7:0] B11; //INPUT B
reg [7:0] B21;
reg [7:0] B31;
reg [7:0] B41;
reg [7:0] B51;
reg [7:0] B21;
reg [7:0] B22;
reg [7:0] B23;
reg [7:0] B24;
reg [7:0] B25;
reg [7:0] B31;
reg [7:0] B32;
reg [7:0] B33;
reg [7:0] B34;
reg [7:0] B35;
reg [7:0] B41;
reg [7:0] B42;
reg [7:0] B43;
reg [7:0] B44;
reg [7:0] B45;
reg [7:0] B51;
reg [7:0] B52;
reg [7:0] B53;
reg [7:0] B54;
reg [7:0] B55;
reg [15:0] C11; //OUTPUTC
reg [15:0] C12;
reg [15:0] C13;
reg [15:0] C14;
reg [15:0] C15;
reg [15:0] C21;
reg [15:0] C22;
reg [15:0] C23;
reg [15:0] C24;
reg [15:0] C25;
reg [15:0] C31;
reg [15:0] C32;
reg [15:0] C33;
reg [15:0] C34;
reg [15:0] C35;
reg [15:0] C41;
reg [15:0] C42;
reg [15:0] C43;
reg [15:0] C44;
reg [15:0] C45;
reg [15:0] C51;
reg [15:0] C52;
reg [15:0] C53;
reg [15:0] C54;
reg [15:0] C55;
always@( A or B)
begin
i=0;
j=0;
k=0;
for(i=0;i<5;i++)
for(j=0;j<5;j++)
data [A][B] = 8'h00;
end
 
C11 = A11*B11 + A12*B21 + A13*B31 + A14*B41 + A15*A51 ;
C12 = A11*B12 + A12*B22 + A13*B32 + A14*B42 + A15*B52 ; 
C13 = A11*B13 + A12*B23 + A13*B33 + A14*B43 + A15*B53 ;
C14 = A11*B14 + A12*B24 + A13*B34 + A14*B44 + A15*B54 ;
C15 = A11*B15 + A12*B25 + A13*B35 + A14*B45 + A15*B55 ; 
C21 = A21*B11 + A22*B21 + A23*B31 + A24*B41 + A25*B51 ;
C22 = A21*B12 + A22*B22 + A23*B32 + A24*B42 + A25*B52 ;
C23 = A21*B13 + A22*B23 + A23*B33 + A24*B43 + A25*B53 ;
C24 = A21*B14 + A22*B24 + A23*B34 + A24*B44 + A25*B54 ;
C25 = A21*B15 + A22*B25 + A23*B35 + A24*B45 + A25*B55 ;
C31 = A31*B11 + A32*B21 + A33*B31 + A34*B41 + A35*B51 ;
C32 = A31*B12 + A32*B22 + A33*B32 + A34*B42 + A35*B52 ;
C33 = A31*B13 + A32*B23 + A33*B33 + A34*B43 + A35*B53 ;
C34 = A31*B14 + A32*B24 + A33*B34 + A34*B44 + A35*B54 ;
C35 = A31*B15 + A32*B25 + A33*B35 + A34*B45 + A35*B55 ;
C41 = A41*B11 + A42*B21 + A43*B31 + A44*B41 + A45*B51 ;
C42 = A41*B12 + A42*B22 + A43*B32 + A44*B42 + A45*B52 ;
C43 = A41*B13 + A42*B23 + A43*B33 + A44*B43 + A45*B53 ;
C44 = A41*B14 + A42*B24 + A43*B34 + A44*B44 + A45*B54 ;
C45 = A41*B15 + A42*B25 + A43*B35 + A44*B45 + A45*B55 ;
C51 = A51*B11 + A52*B21 + A53*B31 + A54*B41 + A55*B51 ;
C52 = A51*B12 + A52*B22 + A23*B32 + A54*B42 + A55*B52 ;
C53 = A51*B13 + A52*B23 + A53*B33 + A54*B43 + A55*B53 ;
C54 = A51*B14 + A52*B24 + A53*B34 + A54*B44 + A55*B54 ;
C55 = A51*B15 + A52*B25 + A53*B35 + A54*B45 + A55*B55 ;
end
end module
 

Wow, you are off by a lot. You need to learn to code synthesizable verilog. You need to learn to code FSMs that implement some sort of control logic for the multiplication.
 

the input/output appears to be 8-16 bits. I don't see anything in the interface that describes how A/B/C are intended to be transmitted.

C might need to be 19bits -- 8b*8b would give 16b results, but then you add five of these together. Depending on the values of A, B, the resulting C values could be larger than 16b.

The code as listed has 125 small multipliers. This is fine if you need this to complete every cycle, but the input don't appear to be set up to do this.

The A11-A55, B11-B55 are never set, and C11-C55 are never used.
 

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