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[Verilog] Asynchronous Reset

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EEPuppyPuppy

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Code: 
module  asyn_reset(clk,reset,a,c);
     input clk;
     input reset;
     input a;
     output c; 

   wire clk;
   wire reset;   
   wire a;    
   reg c;
        
always @ (posedge clk or posedge reset)
 if ( reset == 1'b1) begin
   c <= 0;
 end else begin
   c <= a;
 end
endmodule

Above is the code from asic world (https://www.asic-world.com/code/tidbits/asyn_reset.v)
I am confused for the 'always @' and 'if' part about 'reset'.
Since 'always @' holds the condition when we check the if loop. One of the condition is at the rising edge of reset.
If only consider reset, when it is at its rising edge, reset might hold the value from 0 to 1 inclusive. Thus, reset might be some value in between 0 and 1, such as 0.3, when reset hasn't reached 1 yet if it rises slowly.
In this case, reset == 1 condition would fail and reset would fail.

Could anyone please explain this to me?
Thank you so much!
 

Your code will synthesize to logic for an asynchronous reset, no edge detection is involved in the hardware for the reset signal.
You should view the verilog code as instructions to the simulator about how to simulate an asynchronous reset.
The simulator will execute the code in the always block when there is a positive edge on clk or reset. In simulation reset is guaranteed to be '1' after a rising edge.
Remember that both verilog and VHDL were designed to simulate a hardware design. Synthesis came later.
For an asynchronous reset, it is easier to see the correlation between source code and synthesized hardware with VHDL.
 

I will suggest you to take a look at D flip flop internal structure and see how asyn reset factors into output. Coming back to your question, if switching delay of reset from 0 -> 1 is extremely slow in that case actual circuit will not reset until reset is logically 1. Also from simulator perspective, it follows zero delay modelling and hence, it is not an issue for simulators.
 

std_match said:
Your code will synthesize to logic for an asynchronous reset, no edge detection is involved in the hardware for the reset signal.
You should view the verilog code as instructions to the simulator about how to simulate an asynchronous reset.
The simulator will execute the code in the always block when there is a positive edge on clk or reset. In simulation reset is guaranteed to be '1' after a rising edge.
Remember that both verilog and VHDL were designed to simulate a hardware design. Synthesis came later.
For an asynchronous reset, it is easier to see the correlation between source code and synthesized hardware with VHDL.
Click to expand...

Thanks for your response.

Do you mean that during the simulation, 'always @' will compile first and the if loop will compile after that?
So while the simulator reaches the line 'if (reset == 1'b1)', the 'posedge reset' has been checked and reset has rised up to 1 already.
Therefore, if I want to reset the circuit and change reset value from 0 to 1, when the compiler reach 'if (reset == 1'b1)', the reset value here is the one after the rising edge, which is 1.

When you say there is no edge detection involved, do you mean there is no Verilog code for edge detection component? I am wondering why 'always @ posedge' is not edge dection?
 

EEPuppyPuppy said:
Thanks for your response.

Do you mean that during the simulation, 'always @' will compile first and the if loop will compile after that?
So while the simulator reaches the line 'if (reset == 1'b1)', the 'posedge reset' has been checked and reset has rised up to 1 already.
Therefore, if I want to reset the circuit and change reset value from 0 to 1, when the compiler reach 'if (reset == 1'b1)', the reset value here is the one after the rising edge, which is 1.

When you say there is no edge detection involved, do you mean there is no Verilog code for edge detection component? I am wondering why 'always @ posedge' is not edge dection?
Click to expand...

forget about interpreting the code line by line like software. verilog is about templates. the way that specific code was written implies an async reset and that is all that matters.
 

forget about interpreting the code line by line like software. verilog is about templates. the way that specific code was written implies an async reset and that is all that matters.
Click to expand...
Yes, it's the required template for synchronous registers with asynchronous reset, understood by all synthesis tools. Interpreting the code line by line like a simulator shouldn't contradict the synthesis result, but in special cases it does as discussed in previous Edaboard threads, e.g. when having multiple asynchronous inputs.

https://www.edaboard.com/showthread.php?321110-Sensitivity-lists-syntax-in-VHDL-and-Verilog
https://www.edaboard.com/showthread.php?360120-asynchronous-reset-signal-in-sensitive-list
https://www.edaboard.com/showthread.php?369879-VHDL-equivalent-of-Verilog-code

Referring to the original question, it's useless and misleading to read a behavior into the register template that's neither intended nor supported by the logic hardware. The hardware doesn't perform edge detection for multiple inputs and it doesn't detect other logic levels than 0 and 1.
 

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