Altera Cyclone IV Internal Memory - ROM: 1-Port Problem

Hi,

I have created a MIF file containing 100 x 16bit values. The values point to a colour palette which contains the RGB values for 10 colours.

In Quartus Prime Lite I have used the IP Catalogue to create a ROM: 1-Port file

My top Verilog HDL file references the ROM file which when compiled / simulated on the FPGA development board should produce a 10 coloured stripped square (10 x 10 pixels) on the attached monitor. However, all I get is a blue square.

Could you please help me with where my code is going wrong. After I compile the design the total memory bits states 4 / 423,936 ( < 1 % ), which I believe is not right for the size of the data I am trying to place in the ROM memory.

I have attached the files for my design (in .txt format). Please ignore the 640x480 file name references, it should actually be 800x600

The spiterom module isn't referenced because variable address isn't driven in the design. Instead it must be connected to clk.
Accessing q as an array is also wrong. You get the memory value according to variable address back in variable q.

You'll notice that ROM value q is delayed relative to address.

The best way to check the operation of your design step-by-step is to use Modelsim.

Many, many thanks for the reply.

So my code;


Is this correct or should I be using "clk" instead of "clock".

During the

is it possible to read the ROM during this period and output it via "red" , "green" and "blue".

I understand what you say about q. Would you be able to provide me with some code showing how to do it correctly please.