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Simulating Mos varctor

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Gurjar

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I am getting the same Cgg for the post lay out simulation and schematic simulation in the range of few fF for a 10 finger PMOS. Is something wrong with my lay out?
please answer.....
 

Many reason can be, but I think the main is that Cgg is inside parameter of the MOS transistor, the model contains it and MOS operating point can shift its value.
The extracted parasitic capacitors from the layout are added to the nets (so you can find those in the netlist) and the Cgg won't affected. There isn't too much relationship between Cgg and layout wiring parasitics.
 

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